#define CONFIG_APPNAME6 "BOCHS "
#define CONFIG_APPNAME4 "BXPC"
+// Configure for use with KVM.
+#define CONFIG_KVM 0
// Configure as a coreboot payload.
#define CONFIG_COREBOOT 0
#define CONFIG_PS2_MOUSE 1
// Support for IDE disk code
#define CONFIG_ATA 1
-// Support calling int155f on each keyboard press
+// Support calling int155f on each keyboard event
#define CONFIG_KBD_CALL_INT15_4F 1
// Support for booting from a CD
#define CONFIG_CDROM_BOOT 1
#define CONFIG_CDROM_EMU 1
// Support int 1a/b1 PCI BIOS calls
#define CONFIG_PCIBIOS 1
-// Maximum number of PCI busses.
-#define CONFIG_PCI_BUS_COUNT 2
// Support int 15/53 APM BIOS calls
#define CONFIG_APMBIOS 1
+// Support PnP BIOS entry point.
+#define CONFIG_PNPBIOS 1
// Support int 19/18 system bootup support
#define CONFIG_BOOT 1
-// Support int 14 parallel port calls
+// Support int 14 serial port calls
#define CONFIG_SERIAL 1
// Support int 17 parallel port calls
#define CONFIG_LPT 1
#define CONFIG_KEYBOARD 1
// Support finding and running option roms during post.
#define CONFIG_OPTIONROMS 1
+// Set if option roms are already copied to 0xc0000-0xf0000
+#define CONFIG_OPTIONROMS_DEPLOYED 1
+// When option roms are not pre-deployed, SeaBIOS can copy an optionrom
+// from flash for up to 2 devices.
+#define OPTIONROM_BDF_1 0x0000
+#define OPTIONROM_MEM_1 0x00000000
+#define OPTIONROM_BDF_2 0x0000
+#define OPTIONROM_MEM_2 0x00000000
// Support an interactive boot menu at end of post.
#define CONFIG_BOOTMENU 1
// Support generation of ACPI tables (for emulators)
#define CONFIG_ACPI 1
// Support bios callbacks specific to via vgabios.
-#define CONFIG_VGAHOOKS 1
+#define CONFIG_VGAHOOKS 0
// Maximum number of map entries in the e820 map
#define CONFIG_MAX_E820 32
#define CONFIG_BIOS_REVISION 0x01
// Various memory addresses used by the code.
-#define BUILD_STACK_ADDR 0xfffe
-#define BUILD_CPU_COUNT_ADDR 0xf000
-#define BUILD_AP_BOOT_ADDR 0x10000
-#define BUILD_BIOS_ADDR 0xf0000
-#define BUILD_BIOS_SIZE 0x10000
- /* 64 KB used to copy the BIOS to shadow RAM */
-#define BUILD_BIOS_TMP_ADDR 0x30000
+#define BUILD_STACK_ADDR 0x7c00
+#define BUILD_S3RESUME_STACK_ADDR 0x1000
+#define BUILD_AP_BOOT_ADDR 0x10000
+#define BUILD_BIOS_ADDR 0xf0000
+#define BUILD_BIOS_SIZE 0x10000
+// 64 KB used to copy the BIOS to shadow RAM
+#define BUILD_BIOS_TMP_ADDR 0x30000
-#define BUILD_PM_IO_BASE 0xb000
-#define BUILD_SMB_IO_BASE 0xb100
-#define BUILD_SMI_CMD_IO_ADDR 0xb2
+#define BUILD_APIC_ADDR 0xfee00000
+#define BUILD_IOAPIC_ADDR 0xfec00000
-// Start of fixed addresses in 0xf0000 segment.
-#define BUILD_START_FIXED 0xe050
+#define BUILD_SMM_INIT_ADDR 0x38000
+#define BUILD_SMM_ADDR 0xa8000
+#define BUILD_SMM_SIZE 0x8000
// Important real-mode segments
+#define SEG_IVT 0x0000
+#define SEG_BDA 0x0040
#define SEG_BIOS 0xf000
-#define SEG_EBDA 0x9fc0
-#define SEG_BDA 0x0000
-// Segment definitions in 32bit mode.
-#define SEG32_MODE32_CS (2 << 3) // 0x10
-#define SEG32_MODE32_DS (3 << 3) // 0x18
-#define SEG32_MODE16_CS (4 << 3) // 0x20
-#define SEG32_MODE16_DS (5 << 3) // 0x28
+// Segment definitions in protected mode (see rombios32_gdt in romlayout.S)
+#define SEG32_MODE32_CS (2 << 3)
+#define SEG32_MODE32_DS (3 << 3)
+#define SEG32_MODE16_CS (4 << 3)
+#define SEG32_MODE16_DS (5 << 3)
+#define SEG32_MODE16BIG_CS (6 << 3)
+#define SEG32_MODE16BIG_DS (7 << 3)
// Debugging levels. If non-zero and CONFIG_DEBUG_LEVEL is greater
// than the specified value, then the corresponding irq handler will
#define DEBUG_ISR_74 9
#define DEBUG_ISR_75 1
#define DEBUG_ISR_76 10
-#define DEBUG_ISR_hwirq 30
+#define DEBUG_ISR_hwpic1 1
+#define DEBUG_ISR_hwpic2 1
+#define DEBUG_HDL_pnp 1
#endif // config.h