history/display: backspace logic

[hwmod.git] / src / beh_uart_tx_tb.vhd

diff --git a/src/beh_uart_tx_tb.vhd b/src/beh_uart_tx_tb.vhd
index a02ac726b72fa3ecdc42be0aa2a1a53876552faf..3951f9e0efa043a585bff9243a1defcb1a4e3634 100644 (file)
--- a/src/beh_uart_tx_tb.vhd
+++ b/src/beh_uart_tx_tb.vhd
@@ -8,20 +8,22 @@ end entity beh_uart_tx_tb;
 
 architecture sim of beh_uart_tx_tb is
 
-       constant clk_period  : time := 10ns;
+       constant clk_period  : time := 2ns;
        signal clock : std_logic;
        signal reset : std_logic;
        signal done : std_logic;
        signal newsig : std_logic;
+       signal data : std_logic_vector(7 downto 0);
+       signal serial_out : std_logic;
 begin
        inst : entity work.uart_tx(beh)
        port map (
-                sys_clk => clock,
-                sys_res => reset,
-                --=> txd,
-                --=> tx_data,
-                tx_new => newsig,
-                tx_done => done
+               sys_clk => clock,
+               sys_res => reset,
+               txd => serial_out,
+               tx_data => data,
+               tx_new => newsig,
+               tx_done => done
        );
 
        stimuli : process
@@ -29,6 +31,7 @@ begin
                newsig <= '0';
                wait for 10ns;
                --send 'Hallo Welt'
+               data <= X"42";
                newsig <= '1';
                wait for 1000ns;