architecture sim of beh_pc_communication_tb is
type byte_file_type is file of hbyte;
+ subtype my_string is string(1 to 720);
signal sys_clk : std_logic;
signal sys_res_n : std_logic;
signal btn_a : std_logic;
signal tx_new : std_logic;
signal tx_done : std_logic;
signal rx_new : std_logic;
- signal d_get : std_logic;
- signal d_done : std_logic;
+ signal pc_get : std_logic;
+ signal pc_done : std_logic;
signal rx_data, tx_data : std_logic_vector(7 downto 0);
- signal d_zeile : hzeile;
- signal d_spalte : hspalte;
- signal d_char : hbyte;
+ signal pc_zeile : hzeile;
+ signal pc_spalte : hspalte;
+ signal pc_char : hbyte;
begin
- -- display
+ -- pc_communication
inst : entity work.pc_communication(beh)
port map (
sys_clk => sys_clk,
rx_new => rx_new,
-- History
- d_zeile => d_zeile,
- d_spalte => d_spalte,
- d_get => d_get,
- d_done => d_done,
- d_char => d_char
+ pc_zeile => pc_zeile,
+ pc_spalte => pc_spalte,
+ pc_get => pc_get,
+ pc_done => pc_done,
+ pc_char => pc_char
);
clk : process
end process clk;
stub_history : process
- file f : byte_file_type open read_mode is "../../src/pc_communication.test";
- variable rb : hbyte;
+ file f : text open read_mode is "../../src/pc_communication.test";
+ --variable rb : hbyte;
+ variable rb : character;
+ variable good : boolean;
+ variable i : integer;
+ variable buf : my_string;
+ variable l : line;
begin
- d_done <= '0';
- wait until rising_edge(d_get);
+ --take control of the situation.
+ pc_char <= (others => '0');
+ pc_done <= '0';
+ wait until sys_res_n = '1';
+
+ while not endfile (f) loop
+ readline(f, l);
+ buf := l.all;
+ i := 1;
+ while i < l'length loop
+ pc_done <= '0';
+ wait until rising_edge(pc_get);
+ pc_char <= (others => '0');
+ wait for 300 ns;
+
+ pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+ i := i + 1;
+ pc_done <= '1';
+ wait for 30 ns;
+
+ end loop;
+ end loop;
+
assert not endfile(f) report "test beendet" severity failure;
- read(f, rb);
- wait for 30 ns;
- d_char <= rb;
- d_done <= '1';
- wait for 30 ns;
end process stub_history;
-
stub_uart : process
begin
tx_done <= '0';
- wait until rising_edge(tx_new);
- wait for 90 ns;
- tx_done <= '1'; -- FIXME: why is this unresolved?
- wait for 30 ns;
+ wait until sys_res_n = '1';
+ while true loop
+ tx_done <= '0';
+ wait until rising_edge(tx_new);
+ wait for 300 ns;
+ tx_done <= '1';
+ wait for 30 ns;
+ end loop;
end process stub_uart;
reset_and_button : process
-- we only simulate pressing of button a by now!
sys_res_n <= '0';
btn_a <= '0';
- tx_data <= "00000000";
- rx_data <= "00000000";
- d_zeile <= "0000000";
- d_spalte <= "0000000";
- tx_done <= '0';
+ rx_data <= ( others => '0');
rx_new <= '0';
- d_char <= (others => '0');
wait for 90 ns;
sys_res_n <= '1';
wait for 30 ns;
btn_a <= '1';
- wait for 15 ns;
+ wait for 30 ns;
btn_a <= '0';
- --wait;
- wait for 1000 ns;
- assert false report "test beendet" severity failure;
+ wait;
+ --wait for 1000 ns;
+ --assert false report "test beendet" severity failure;
end process reset_and_button;
end architecture sim;