Via Epia-N and C3: Set ioapic delivery type in Kconfig

[coreboot.git] / src / arch / x86 / lib / ioapic.c

diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index e39fe8fd0ad552001cb9b5aa525feef81ab4a721..e974d7cce68a6ec1bd6ee4a082343dcee129b4e6 100644 (file)
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -79,7 +79,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
                printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
                /* Set IOAPIC ID if it has been specified. */
                io_apic_write(ioapic_base, 0x00,
-                       (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) |
+                       (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) |
                        (ioapic_id << 24));
        }
 
@@ -89,15 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
                ioapic_interrupts = 24;
        printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
 
-// XXX this decision should probably be made elsewhere, and
-// it's the C3, not the EPIA this depends on.
-#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT
-#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
-#else
-#define IOAPIC_INTERRUPTS_ON_FSB
-#endif
-
-#ifdef IOAPIC_INTERRUPTS_ON_FSB
+#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_FSB
        /*
         * For the Pentium 4 and above APICs deliver their interrupts
         * on the front side bus, enable that.
@@ -106,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
        io_apic_write(ioapic_base, 0x03,
                      io_apic_read(ioapic_base, 0x03) | (1 << 0));
 #endif
-#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
        printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
        io_apic_write(ioapic_base, 0x03, 0);
 #endif