allgemein: components fuer die module

[hwmod.git] / quartus / project_gen.tcl

diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl
index 242d42b499b014d7f3e5a7a3d38f6e5759079e9c..d608f1095ae2c18d53d6627aac33711d9748fcfa 100644 (file)
--- a/quartus/project_gen.tcl
+++ b/quartus/project_gen.tcl
@@ -49,6 +49,9 @@ if {$make_assignments} {
        set_global_assignment -name VHDL_FILE ../../src/history.vhd
        set_global_assignment -name VHDL_FILE ../../src/calc.vhd
        set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
+       set_global_assignment -name VHDL_FILE ../../src/uart_tx.vhd
+       set_global_assignment -name VHDL_FILE ../../src/uart_rx.vhd
+       set_global_assignment -name VHDL_FILE ../../src/pc_communication.vhd
        
        #vga ip-core
        set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm.vhd
@@ -118,6 +121,13 @@ if {$make_assignments} {
        set_location_assignment PIN_Y26 -to ps2_clk
        set_location_assignment PIN_E21 -to ps2_data
 
+       #rs232
+       set_location_assignment PIN_D22 -to txd
+       set_location_assignment PIN_D23 -to rxd
+
+       #btn_a
+       set_location_assignment PIN_A3 -to btn_a
+
        set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
        set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
        #warning fix fuer pll