writeback_stage: differenzieren zwischen memory und extension geht ( btw wer sich...

[calu.git] / dt / dt.tan.summary

diff --git a/dt/dt.tan.summary b/dt/dt.tan.summary
index 05647d5ebfa21c22ecc1573a012d110785e37f2b..cb2822c730f55c5ac77ec82b2583deb25930f6b2 100644 (file)
--- a/dt/dt.tan.summary
+++ b/dt/dt.tan.summary
@@ -2,21 +2,41 @@
 Timing Analyzer Summary
 --------------------------------------------------------------------------------------
 
+Type           : Worst-case tsu
+Slack          : N/A
+Required Time  : None
+Actual Time    : 18.965 ns
+From           : sys_res
+To             : fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27]
+From Clock     : --
+To Clock       : sys_clk
+Failed Paths   : 0
+
 Type           : Worst-case tco
 Slack          : N/A
 Required Time  : None
-Actual Time    : 8.846 ns
+Actual Time    : 10.165 ns
 From           : writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int
 To             : bus_tx
 From Clock     : sys_clk
 To Clock       : --
 Failed Paths   : 0
 
+Type           : Worst-case th
+Slack          : N/A
+Required Time  : None
+Actual Time    : -8.849 ns
+From           : sys_res
+To             : fetch_stage:fetch_st|instr_r_addr[4]
+From Clock     : --
+To Clock       : sys_clk
+Failed Paths   : 0
+
 Type           : Clock Setup: 'sys_clk'
 Slack          : N/A
 Required Time  : None
-Actual Time    : 49.70 MHz ( period = 20.119 ns )
-From           : decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2
+Actual Time    : 46.34 MHz ( period = 21.578 ns )
+From           : decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2
 To             : writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4]
 From Clock     : sys_clk
 To Clock       : sys_clk