Fixed some bugs.

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 86015cdb8f4c2ba5922f0f9212a88fd1b2eec3a5..94af88c05e09567d340993b4150934620b50330e 100644 (file)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -2,40 +2,48 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.common_pkg.all;
 use work.core_pkg.all;
 
-architecture behav of writeback_stage is
+use work.mem_pkg.all;
 
+architecture behav of writeback_stage is
 
-begin
 
 signal data_ram_read : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
+begin
+
+
        data_ram : r_w_ram
                generic map (
-                       PHYS_DATA_ADDR_WIDTH,
+                       DATA_ADDR_WIDTH,
                        WORD_WIDTH
                )
                
                port map (
                        clk,
-                       wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
-                       wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
+                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
+                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
                        wb_reg_nxt.dmem_write_en,
                        ram_data,
                        data_ram_read
                );
 
 
-syn: process(sys_clk, reset)
+syn: process(clk, reset)
 
 begin
 
        if (reset = RESET_VALUE) then
-
-       elsif rising_edge(sys_clk) then
+               wb_reg_nxt.address <= (others => '0');
+               wb_reg_nxt.dmem_en <= '0';
+               wb_reg_nxt.dmem_write_en <= '0';
+               wb_reg_nxt.hword <= '0';
+               wb_reg_nxt.byte_s <= '0';
+       elsif rising_edge(clk) then
                wb_reg <= wb_reg_nxt;
        end if;
        
@@ -50,7 +58,7 @@ end process;
 
 
 
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword_hl, wb_reg, result)
+shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result)
 
 begin
        wb_reg_nxt.address <= address;
@@ -78,6 +86,7 @@ begin
                                when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
                                when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
                                when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
+                               when others => null;
                        end case;
                end if; 
        end if;