use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
+use work.common_pkg.all;
use work.core_pkg.all;
+use work.mem_pkg.all;
+use work.extension_pkg.all;
+use work.extension_uart_pkg.all;
+
architecture behav of writeback_stage is
+signal data_ram_read, data_ram_read_ext : word_t;
+signal data_addr : word_t;
-begin
+signal wb_reg, wb_reg_nxt : writeback_rec;
-signal data_ram_read : word_t;
+signal ext_uart,ext_timer,ext_gpmp : extmod_rec;
+
+signal sel_nxt :std_logic;
+
+
+
+begin
-signal wb_reg, wb_reg_nxt : writeback_rec;
data_ram : r_w_ram
generic map (
- PHYS_DATA_ADDR_WIDTH,
+ DATA_ADDR_WIDTH,
WORD_WIDTH
)
port map (
clk,
- wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
- wb_reg_nxt.address(PHYS_DATA_ADDR_WIDTH+1 downto 2),
+ data_addr(DATA_ADDR_WIDTH+1 downto 2),
+ data_addr(DATA_ADDR_WIDTH+1 downto 2),
wb_reg_nxt.dmem_write_en,
ram_data,
data_ram_read
);
+uart : extension_uart
+ generic map(
+ RESET_VALUE
+ )
+ port map(
+ clk ,
+ reset,
+ ext_uart,
+ data_ram_read_ext,
+ bus_tx
+ );
-syn: process(sys_clk, reset)
+
+syn: process(clk, reset)
begin
if (reset = RESET_VALUE) then
-
- elsif rising_edge(sys_clk) then
+ wb_reg.address <= (others => '0');
+ wb_reg.dmem_en <= '0';
+ wb_reg.dmem_write_en <= '0';
+ wb_reg.hword <= '0';
+ wb_reg.byte_s <= '0';
+ elsif rising_edge(clk) then
wb_reg <= wb_reg_nxt;
end if;
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword_hl, wb_reg, result)
+shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en)
begin
wb_reg_nxt.address <= address;
when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
+ when others => null;
end case;
end if;
end if;
- jump <= alu_jmp xor br_pred;
- jump_addr <= result;
- if ((alu_jmp and wb_reg.dmem_en) = '1') then
+ --jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
+ jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en);
+
+ if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
jump_addr <= data_ram_read;
+ else
+ jump_addr <= result;
end if;
+-- if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
+-- jump <= '1';
+-- end if;
+
+-- if ((alu_jmp and wb_reg.dmem_en) = '1') then
+-- jump_addr <= data_ram_read;
+-- end if;
+
end process;
-- result : in gp_register_t; --reg (alu result or jumpaddr)
-out_logic: process(write_en, result_addr)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt)
-begin
- reg_we <= write_en;
+begin
+ reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
reg_addr <= result_addr;
+
+ data_addr <= (others => '0');
+
+ if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) = '1') then
+ data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
+ end if;
+end process;
+
+
+addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg,sel_nxt,wb_reg_nxt.dmem_write_en)
+
+begin
+ ext_uart.sel <='0';
+ ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+ ext_uart.byte_en <= (others => '0');
+ ext_uart.data <= (others => '0');
+ ext_uart.addr <= (others => '0');
+
+ ext_timer.sel <='0';
+ ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
+ ext_timer.byte_en <= (others => '0');
+ ext_timer.data <= (others => '0');
+ ext_timer.addr <= (others => '0');
+
+ ext_gpmp.sel <='0';
+ ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
+ ext_gpmp.byte_en <= (others => '0');
+ ext_gpmp.data <= (others => '0');
+ ext_gpmp.addr <= (others => '0');
+ -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
+ case wb_reg_nxt.address(wb_reg_nxt.address'high downto 4) is
+ when EXT_UART_ADDR =>
+ ext_uart.sel <='1';
+ ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
+ ext_uart.data <= ram_data;
+ ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
+ case wb_reg.address(1 downto 0) is
+ when "00" => ext_uart.byte_en <= "0001";
+ when "01" => ext_uart.byte_en <= "0010";
+ when "10" => ext_uart.byte_en <= "0100";
+ --when "11" => ext_uart.byte_en <= "1000";
+ when "11" => ext_uart.byte_en <= "1111";
+ when others => null;
+ end case;
+ when EXT_TIMER_ADDR =>
+ ext_timer.sel <='1';
+ ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
+ ext_timer.data <= ram_data;
+ ext_timer.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
+ case wb_reg.address(1 downto 0) is
+ when "00" => ext_timer.byte_en <= "0001";
+ when "01" => ext_timer.byte_en <= "0010";
+ when "10" => ext_timer.byte_en <= "0100";
+ when "11" => ext_timer.byte_en <= "1000";
+ when others => null;
+ end case;
+ when EXT_GPMP_ADDR =>
+ ext_gpmp.sel <='1';
+ ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
+ ext_gpmp.data <= ram_data;
+ ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
+ case wb_reg.address(1 downto 0) is
+ when "00" => ext_gpmp.byte_en <= "0001";
+ when "01" => ext_gpmp.byte_en <= "0010";
+ when "10" => ext_gpmp.byte_en <= "0100";
+ when "11" => ext_gpmp.byte_en <= "1000";
+ when others => null;
+ end case;
+ -- hier kann man weiter extensions adden :) Konstanten sind im extension pkg definiert
+ when others => null;
+ end case;
+
end process;
end behav;
projects / calu.git / blobdiff