begin
if (reset = RESET_VALUE) then
- wb_reg_nxt.address <= (others => '0');
- wb_reg_nxt.dmem_en <= '0';
- wb_reg_nxt.dmem_write_en <= '0';
- wb_reg_nxt.hword <= '0';
- wb_reg_nxt.byte_s <= '0';
+ wb_reg.address <= (others => '0');
+ wb_reg.dmem_en <= '0';
+ wb_reg.dmem_write_en <= '0';
+ wb_reg.hword <= '0';
+ wb_reg.byte_s <= '0';
elsif rising_edge(clk) then
wb_reg <= wb_reg_nxt;
end if;
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result)
+shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred)
begin
wb_reg_nxt.address <= address;
-out_logic: process(write_en, result_addr)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
-begin
- reg_we <= write_en;
+begin
+ reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
reg_addr <= result_addr;
end process;