spartan3e: at least it compiles

[calu.git] / cpu / src / writeback_stage.vhd

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 965f996a0a8aa00d21e3824f5e11d3a5e1b1239b..9ec598638530aa97708967dca32b9ac78210de10 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -2,6 +2,8 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.common_pkg.all;
+
 entity writeback_stage is
 
        generic (
@@ -9,12 +11,45 @@ entity writeback_stage is
                        RESET_VALUE : std_logic;
                        -- active logic value
                        LOGIC_ACT : std_logic;
-                       
+                       FPGATYPE : string
                        );
        port(
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+
+                       result : in gp_register_t;      --reg  (alu result or jumpaddr)
+                       result_addr : in gp_addr_t;     --reg
+                       address : in word_t;            --ureg 
+                       ram_data : in word_t;           --ureg
+                       alu_jmp : in std_logic;         --reg
+                       br_pred : in std_logic;         --reg
+                       write_en : in std_logic;        --reg  (register file) bei jump 1 wenn addr in result
+                       dmem_en : in std_logic;         --ureg (jump addr in mem or in address)
+                       dmem_write_en : in std_logic;   --ureg
+                       hword : in std_logic;           --ureg
+                       byte_s : in std_logic;          --ureg  
+
+                       regfile_val : out gp_register_t;
+                       reg_we : out std_logic;
+                       reg_addr : out gp_addr_t;
+                       jump_addr : out instruction_addr_t;
+                       jump : out std_logic;
+                       -- hallo stefan mir adden da jetzt mal schnell an uart port :D
+                       bus_tx : out std_logic;
+                       bus_rx : in std_logic;
+                       -- instruction memory program port :D
+                       new_im_data_out : out std_logic;
+                       im_addr : out gp_register_t;
+                       im_data : out gp_register_t;
+                       
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6);
+
+                       int_req : out interrupt_t
+
                );
                
 end writeback_stage;