gitignore für sim

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 9e530fad63d42eddf6d7b0d6c5204642e408bdd1..f03388593c6ec05dddd76dd1604e820f0a3641f7 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -10,7 +10,11 @@ architecture behaviour of r_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := ((others => b"11100000000000001001000000000000"));
+       signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", 
+                                 1 => "11100000000000001001000000000000", 
+                                 2 => "11100000000010001001000000000000", 
+                                 3 => "11100001000110010111011001101100", 
+                                 others => x"00000000");
 
 begin
        process(clk)