gitignore für sim

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
old mode 100755 (executable)
new mode 100644 (file)
index 50c7660..f033885
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -3,12 +3,18 @@ library ieee;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.mem_pkg.all;
+
 architecture behaviour of r_w_ram is
 
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE; --:= (others=> x"00");
+       signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", 
+                                 1 => "11100000000000001001000000000000", 
+                                 2 => "11100000000010001001000000000000", 
+                                 3 => "11100001000110010111011001101100", 
+                                 others => x"00000000");
 
 begin
        process(clk)