use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
+use work.mem_pkg.all;
+
architecture behaviour of r_w_ram is
subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
- signal ram : RAM_TYPE; --:= (others=> x"00");
-
+ signal ram : RAM_TYPE := (others => x"00000000");
+
begin
process(clk)
begin
if rising_edge(clk) then
- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+ data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+
+
if wr_en = '1' then
ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
end if;
end if;
end process;
+
end architecture behaviour;