timer: added as extension modul

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index f03388593c6ec05dddd76dd1604e820f0a3641f7..a120a29dd6263a1f5226ad2e1ff4f5236a7de1a0 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -10,21 +10,20 @@ architecture behaviour of r_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", 
-                                 1 => "11100000000000001001000000000000", 
-                                 2 => "11100000000010001001000000000000", 
-                                 3 => "11100001000110010111011001101100", 
-                                 others => x"00000000");
-
+       signal ram : RAM_TYPE := (others => x"00000000");
+       
 begin
        process(clk)
        begin
                if rising_edge(clk) then
-                       data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+                data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+
+
                        
                        if wr_en = '1' then
                                ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
                        end if;
                end if;
        end process;
+       
 end architecture behaviour;