2nd forward unit - 58MHz with 31bit shift...

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 9e530fad63d42eddf6d7b0d6c5204642e408bdd1..45779da81a912c35414cb7517c0f4dbe3d5249df 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -10,7 +10,16 @@ architecture behaviour of r_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := ((others => b"11100000000000001001000000000000"));
+       signal ram : RAM_TYPE := (--0 => "11100000000000011001000000000000",  -- r0 = r3 + r2 (always)
+                               --  1 => "11100101000000001000100000000000",  -- r0 = r1 << 0 (always)
+                               --  2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
+                               --  3 => "11100000101000000001000000000000",
+                               --  4 => "11100001000110010111011001101100", 
+                                 0 => "11101100000000001000000000000000", -- cmp r0 , r1 
+                                 1 => "00000000000100000000100000000000",
+                                 2 => "00000000001110000001000000000000",
+                                 3 => "11100001000110010000011001101100", 
+                                 others => x"F0000000");
 
 begin
        process(clk)