uart und extension anbindung

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index aafbd4c91b3e71088ae8f42178588dc0d3d59d96..e396a6bd78f74079dde3c37d25edb765f2c4b735 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -18,8 +18,10 @@ end pipeline_tb;
 -------------------------------------------------------------------------------
 architecture behavior of pipeline_tb is
 
-       constant cc : time := 30 ns;        -- test clock period
-       
+       constant cc : time := 20 ns;        -- test clock period
+       constant SYS_CLOCK_FREQ : integer := 50000000;
+       constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200;
+
                signal sys_clk_pin : std_logic;
                signal sys_res_n_pin : std_logic;
                --Data input
@@ -48,9 +50,16 @@ architecture behavior of pipeline_tb is
                  signal dmem_pin  : std_logic;--memop
                  signal dmem_wr_en_pin : std_logic;
                  signal hword_pin  : std_logic;
-                 signal byte_s_pin : std_logic;
+                 signal byte_s_pin, tx_pin, rx_pin : std_logic;
+                                
+                                 signal gpm_in_pin : extmod_rec;
+                                signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
 
+                signal cycle_cnt : integer;
+
+               signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
+
 
 begin
 
@@ -121,14 +130,14 @@ begin
                );
           exec_st : execute_stage
                 generic map('0')
-                port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
-                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
+                port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
           writeback_st : writeback_stage
                 generic map('0', '1')
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3);
 
 
 
@@ -146,6 +155,18 @@ begin
     wait for cc/2;
   end process CLKGEN;
   
+
+  cnt : process(sys_clk_pin, sys_res_n_pin)
+
+  begin
+
+       if (sys_res_n_pin = '0') then
+               cycle_cnt <= 0;
+       elsif (sys_clk_pin'event and sys_clk_pin = '1') then
+               cycle_cnt <= cycle_cnt + 1;
+       end if;
+
+  end process cnt;
 -------------------------------------------------------------------------------
 -- test the design
 -------------------------------------------------------------------------------
@@ -158,6 +179,17 @@ begin
         wait until sys_clk_pin = '1' and sys_clk_pin'event;
       end loop;
     end;
+
+       procedure txd(trans_data : in std_logic_vector) is
+       begin
+               for i in 0 to 9 loop
+                       rx_pin <= trans_data(i);
+                       dummy <= not dummy;
+                       wait on dummy;
+                       icwait(BAUD_COUNT);
+               end loop;
+       end txd;
+
        
   begin
     -----------------------------------------------------------------------------
@@ -173,8 +205,11 @@ begin
        sys_res_n_pin <= '1';
        wait until sys_res_n_pin = '1';
        
+       icwait(10);
+
+       txd("0100000101");
 
-       icwait(100000);
+       icwait(1000000000);
 
     ---------------------------------------------------------------------------
     -- exit testbench