erster versuch das ganze mal zu flashen -> es blinkt!!111

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index e856e69ec98343498a5a36bc4c5846c24a22a541..d87cee18d26c4f271b2cc9e479f89c26840b2d72 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -4,7 +4,7 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.core_pkg.all;
-
+use work.extension_pkg.all;
 -------------------------------------------------------------------------------
 -- ENTITY
 -------------------------------------------------------------------------------
@@ -31,12 +31,32 @@ architecture behavior of pipeline_tb is
                signal branch_prediction_bit_pin : std_logic;
                signal alu_jump_bit_pin : std_logic;
                signal instruction_pin : instruction_word_t;
+               signal prog_cnt : instruction_addr_t;
 
                signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                signal reg_wr_data_pin : gp_register_t;
                signal reg_we_pin : std_logic;
                signal to_next_stage_pin : dec_op;
 
+                 signal result_pin : gp_register_t;--reg
+                 signal result_addr_pin : gp_addr_t;--reg
+                 signal addr_pin : word_t; --memaddr
+                 signal data_pin : gp_register_t; --mem data --ureg
+                 signal alu_jump_pin : std_logic;--reg
+                 signal brpr_pin  : std_logic;  --reg
+                 signal wr_en_pin : std_logic;--regop --reg
+                 signal dmem_pin  : std_logic;--memop
+                 signal dmem_wr_en_pin : std_logic;
+                 signal hword_pin  : std_logic;
+                 signal byte_s_pin : std_logic;
+                                
+                                 signal gpm_in_pin : extmod_rec;
+                                signal gpm_out_pin : gp_register_t;
+                signal nop_pin : std_logic;
+
+                signal cycle_cnt : integer;
+
+
 begin
 
 --             instruction_ram : r_w_ram
@@ -73,8 +93,9 @@ begin
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
 
                --Data outputs
-                       instruction => instruction_pin --: out instruction_word_t
-               );
+                       instruction => instruction_pin, --: out instruction_word_t
+                       prog_cnt => prog_cnt
+               );      
 
        decode_st : decode_stage
                generic map (
@@ -91,9 +112,11 @@ begin
 
                --Data inputs
                        instruction => instruction_pin, --: in instruction_word_t;
+                       prog_cnt => prog_cnt,
                        reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                        reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
                        reg_we => reg_we_pin, --: in std_logic;
+                       nop => nop_pin,
 
                --Data outputs
                        branch_prediction_res => prediction_result_pin, --: instruction_word_t;
@@ -101,8 +124,21 @@ begin
                        to_next_stage => to_next_stage_pin
                        
                );
+          exec_st : execute_stage
+                generic map('0')
+                port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
+
+          writeback_st : writeback_stage
+                generic map('0', '1')
+                port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+
+
 
 
+       nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin);
 
 -------------------------------------------------------------------------------
 -- generate simulation clock
@@ -115,6 +151,18 @@ begin
     wait for cc/2;
   end process CLKGEN;
   
+
+  cnt : process(sys_clk_pin, sys_res_n_pin)
+
+  begin
+
+       if (sys_res_n_pin = '0') then
+               cycle_cnt <= 0;
+       elsif (sys_clk_pin'event and sys_clk_pin = '1') then
+               cycle_cnt <= cycle_cnt + 1;
+       end if;
+
+  end process cnt;
 -------------------------------------------------------------------------------
 -- test the design
 -------------------------------------------------------------------------------
@@ -133,9 +181,9 @@ begin
     -- initial reset
     -----------------------------------------------------------------------------
        sys_res_n_pin <= '0';
-       reg_w_addr_pin <= (others => '0');
-       reg_wr_data_pin <= (others => '0');
-       reg_we_pin <= '0';
+--     reg_w_addr_pin <= (others => '0');
+--     reg_wr_data_pin <= (others => '0');
+--     reg_we_pin <= '0';
 
        icwait(10);
        dummy <= '1';
@@ -143,7 +191,7 @@ begin
        wait until sys_res_n_pin = '1';
        
 
-       icwait(100000);
+       icwait(1000000000);
 
     ---------------------------------------------------------------------------
     -- exit testbench
@@ -166,6 +214,10 @@ configuration pipeline_conf_beh of pipeline_tb is
     end for;
     for decode_st : decode_stage use entity work.decode_stage(behav);
     end for;
+    for exec_st : execute_stage use entity work.execute_stage(behav);
+    end for;
+    for writeback_st : writeback_stage use entity work.writeback_stage(behav);
+    end for;
 
   end for;
 end pipeline_conf_beh;