spartan3e: BRAM gehaxe. lesbarer und wird auch richtig(er) instanziert

[calu.git] / cpu / src / mem_pkg.vhd

diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd
old mode 100755 (executable)
new mode 100644 (file)
index cba7fd6..425af91
--- a/cpu/src/mem_pkg.vhd
+++ b/cpu/src/mem_pkg.vhd
@@ -23,8 +23,46 @@ package mem_pkg is
                        data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
        end component r_w_ram;
-       
-       component r2_w_ram is
+
+       component r_w_ram_be is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               clk : in std_logic;
+
+               waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+               be : in std_logic_vector (3 downto 0);
+               
+               we : in std_logic;
+
+               wdata : in std_logic_vector(31 downto 0);
+               
+               q : out std_logic_vector(31 downto 0)
+       );
+       end component r_w_ram_be;
+
+       component ram_xilinx is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               clk : in std_logic;
+
+               waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+               be : in std_logic_vector (3 downto 0);
+               
+               we : in std_logic;
+
+               wdata : in std_logic_vector(31 downto 0);
+               
+               q : out std_logic_vector(31 downto 0)
+       );
+       end component ram_xilinx;
+
+       component rom is
        generic (
                                ADDR_WIDTH : integer range 1 to integer'high;
                                DATA_WIDTH : integer range 1 to integer'high
@@ -33,17 +71,13 @@ package mem_pkg is
                --System inputs
                        clk : in std_logic;
                --Input
-                       wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-                       
-                       wr_en : in std_logic;
-                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
-                       
+                       rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);                   
                --Output
-                       data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+                       data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
-       end component r2_w_ram;
+       end component rom;
        
-       component rw2_ram is
+       component r2_w_ram is
        generic (
                                ADDR_WIDTH : integer range 1 to integer'high;
                                DATA_WIDTH : integer range 1 to integer'high
@@ -58,11 +92,11 @@ package mem_pkg is
                        data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
                        
                --Output
-                       out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+                       data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
-       end component rw2_ram;
+       end component r2_w_ram;
        
-       component rw_ram is
+       component rw_r_ram is
        generic (
                                ADDR_WIDTH : integer range 1 to integer'high;
                                DATA_WIDTH : integer range 1 to integer'high
@@ -71,14 +105,14 @@ package mem_pkg is
                --System inputs
                        clk : in std_logic;
                --Input
-                       wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+                       rw_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
                        
                        wr_en : in std_logic;
                        data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
                        
                --Output
-                       out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+                       rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
-       end component rw_ram;
+       end component rw_r_ram;
 
 end package mem_pkg;