static branch incl prediction rc1

[calu.git] / cpu / src / fetch_stage_b.vhd

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index 2dd8e92446af2123e53a0596a918882bf47bb731..7409e426989e699a755b92f03fd4ae3774919bae 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 
 use work.core_pkg.all;
 use work.common_pkg.all;
+use work.mem_pkg.all;
 
 architecture behav of fetch_stage is
 
@@ -23,7 +24,7 @@ begin
                )
                
                port map (
-                       sys_clk,
+                       clk,
                        instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
                        instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
                        instr_we,
@@ -31,33 +32,41 @@ begin
                        instr_rd_data
                );
 
-syn: process(sys_clk, reset)
+syn: process(clk, reset)
 
 begin
 
        if (reset = RESET_VALUE) then
                instr_r_addr <= (others => '0');
-       elsif rising_edge(sys_clk) then
+       elsif rising_edge(clk) then
                instr_r_addr <= instr_r_addr_nxt;               
        end if;
        
 end process; 
 
 
-asyn: process(instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit)
+asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
 
 begin
 
        instruction <= instr_rd_data;
        instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
 
+       if (reset = RESET_VALUE) then
+               instr_r_addr_nxt <= (others => '0');
+       end if;
+
        if (alu_jump_bit = LOGIC_ACT) then
-               instr_r_addr_nxt <= jump_result;        
+               instr_r_addr_nxt <= jump_result;
+               instruction(31 downto 28) <= "1111";    
        elsif (branch_prediction_bit = LOGIC_ACT) then
                instr_r_addr_nxt <= prediction_result;
        end if; 
 
 end process;
 
+prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
+prog_cnt(31 downto 11) <= (others => '0');
+
 end behav;