library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.core_pkg.all;
use work.common_pkg.all;
use work.mem_pkg.all;

architecture behav of fetch_stage is

signal instr_w_addr 	 : instruction_addr_t;
signal instr_r_addr  	 : instruction_addr_t;
signal instr_r_addr_nxt  : instruction_addr_t;
signal instr_we      	 : std_logic;
signal instr_wr_data 	 : instruction_word_t;
signal instr_rd_data 	 : instruction_word_t;

begin

	instruction_ram : r_w_ram
		generic map (
			PHYS_INSTR_ADDR_WIDTH,
			WORD_WIDTH
		)
		
		port map (
			clk,
			instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
			instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
			instr_we,
			instr_wr_data,
			instr_rd_data
		);

syn: process(clk, reset)

begin

	if (reset = RESET_VALUE) then
		instr_r_addr <= (others => '0');
	elsif rising_edge(clk) then
		instr_r_addr <= instr_r_addr_nxt;		
	end if;
	
end process; 


asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)

begin

	instruction <= instr_rd_data;
	instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);

	if (reset = RESET_VALUE) then
		instr_r_addr_nxt <= (others => '0');
	end if;

	if (alu_jump_bit = LOGIC_ACT) then
		instr_r_addr_nxt <= jump_result;
		instruction(31 downto 28) <= "1111";	
	elsif (branch_prediction_bit = LOGIC_ACT) then
		instr_r_addr_nxt <= prediction_result;
	end if;	

end process;

prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
prog_cnt(31 downto 11) <= (others => '0');

end behav;