--constant CLK_FREQ_MHZ : real := 33.33;
--constant BAUD_RATE : integer := 115200;
--constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
-constant CLK_PER_BAUD : integer := 434;
+-- constant CLK_PER_BAUD : integer := 434;
+-- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 50; -- @modelsim
component extension_uart is
--some modules won't need all inputs/outputs
generic (
-- active reset value
- RESET_VALUE : std_logic
+ RESET_VALUE : std_logic;
+ CLK_PER_BAUD : integer
);
port(
--System inputs
-- general extension interface
ext_reg : in extmod_rec;
data_out : out gp_register_t;
+
+ uart_int : out std_logic;
-- Input
bus_rx : in std_logic;
-- Ouput
component rs232_rx is
generic (
-- active reset value
- RESET_VALUE : std_logic
+ RESET_VALUE : std_logic;
+ SYNC_STAGES : integer range 2 to integer'high
);
port(
sys_res_n : in std_logic;
--Bus
- bus_rx : in std_logic;
+ bus_rx_unsync : in std_logic;
--To sendlogic
new_rx_data : out std_logic;