uart und extension anbindung

[calu.git] / cpu / src / extension_uart_b.vhd

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index bf29728f6ee4024a393425f44deec36084a9a56a..45150df71a87a78286eb50fdb4e716f9cc27a23f 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -12,9 +12,9 @@ use work.extension_uart_pkg.all;
 architecture behav of extension_uart is
 
 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
-signal new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
+signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
 signal         bd_rate : baud_rate_l;
-
+signal rx_data : std_logic_vector(7 downto 0);
 begin
 
 
@@ -38,6 +38,24 @@ port map(
        w1_st_co(0)
 );
 
+rs232_rx_inst : rs232_rx
+generic        map(
+               RESET_VALUE,
+               2
+               )
+port map(
+       --System inputs
+       clk,
+       reset,
+
+       --Bus
+       bus_rx,
+
+       --From/to sendlogic
+       new_bus_rx,
+       rx_data,
+       bd_rate
+);
 
 
 
@@ -46,10 +64,13 @@ syn : process (clk, reset)
 begin
         if (reset = RESET_VALUE) then
                w1_st_co <= (others=>'0');
-               w2_uart_config <= (others=>'0');
+               w2_uart_config(31 downto 16) <= (others=>'0');
+               -- todo mit einer konstante versehen
+               w2_uart_config(15 downto 0) <= x"01B2";
                w3_uart_send <= (others=>'0');
                w4_uart_receive <= (others=>'0');
-
+               tx_rdy_int <= '0';
+               new_tx_data <= '0';
 
         elsif rising_edge(clk) then            
                w1_st_co <= w1_st_co_nxt;
@@ -63,7 +84,7 @@ end process syn;
 
 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
 
-gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int)
+gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx)
 
 variable tmp_data  : gp_register_t;
 
@@ -98,7 +119,7 @@ begin
                        w1_st_co_nxt(16) <= '1'; -- busy flag set
                        w3_uart_send_nxt <= tmp_data;
                when "11" =>
-                       w4_uart_receive_nxt <= tmp_data;
+                       --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
                when others => null;
                end case;
        end if;
@@ -107,6 +128,12 @@ begin
                w1_st_co_nxt(16) <= '0'; -- busy flag reset     
        end if;
 
+       if new_bus_rx = '1' then
+               w4_uart_receive_nxt(7 downto 0) <= rx_data;
+               w1_st_co_nxt(17) <= '1';
+       end if;
+       
+
 end process gwriten;
 
 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)