kleine Änderungen

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 095d4dc5e813bc1a00a3be9882ca5d49261199cc..73c7bf27e638d8cc0a063306cf22117f82f80d5f 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.alu_pkg.all;
+use work.gpm_pkg.all;
 
 architecture behav of execute_stage is
 
@@ -12,50 +13,98 @@ signal op_group : op_info_t;
 signal op_detail : op_opt_t;
 signal left_operand, right_operand : gp_register_t;
 signal alu_state, alu_nxt : alu_result_rec;
-
 signal psw : status_rec;
 
+type exec_internal is record
+        result : gp_register_t;
+        res_addr : gp_addr_t;
+        alu_jump : std_logic;
+        brpr    : std_logic;
+        wr_en   : std_logic;
+end record;
+
+signal reg, reg_nxt : exec_internal;
+
 begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-        op_detail, left_operand, right_operand, alu_state, alu_nxt);
+         left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data);
 
-syn: process(sys_clk, reset)
+gpm_inst : gpm
+        generic map(RESET_VALUE)
+        port map(clk,reset,alu_nxt,psw);
+
+syn: process(clk, reset)
 
 begin
 
-       if (reset = RESET_VALUE) then
-               condition <=                    
-       elsif rising_edge(sys_clk) then
-               
+       if reset = RESET_VALUE then
+               reg.alu_jump <= '0';
+                reg.brpr <= '0';
+                reg.wr_en <= '0';
+                reg.result <= (others =>'0');
+                reg.res_addr <= (others => '0');                       
+       elsif rising_edge(clk) then
+               reg <= reg_nxt;
        end if;
        
 end process;
 
-asyn: process(reset,condition)
+asyn: process(reset,dec_instr, alu_nxt, psw, reg,left_operand,right_operand)
 begin
 
         condition <= dec_instr.condition;
         op_group <= dec_instr.op_group;
         op_detail <= dec_instr.op_detail;
-        left_operand <= dec_instr.src1;
-        right_operand <= dec_instr.src2;
+        
 
-        alu_state.status <= psw;
-        alu_state.result_addr <= dec_instr.daddr;
-        alu_state.brpr <= brpr;
-        alu_state.reg_op <= '0';
-        alu_state.mem_op <= '0';
-        alu_state.
+
+        alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0'); 
+        
 
         if reset = RESET_VALUE then
                 condition <= COND_NEVER;
         else
                 
         end if;
+        
+        reg_nxt.brpr <= alu_nxt.brpr;
+        reg_nxt.alu_jump <= alu_nxt.alu_jump;
+        reg_nxt.wr_en <= alu_nxt.reg_op;
+        reg_nxt.result <= alu_nxt.result;
+        reg_nxt.res_addr <= alu_nxt.result_addr;
 
 end process asyn;
 
+forward: process(regfile_val, reg_we, reg_addr, dec_instr)
+begin
+       left_operand <= dec_instr.src1;
+        right_operand <= dec_instr.src2;
+
+       if reg_we = '1' then
+               if dec_instr.saddr1 = reg_addr then
+                       left_operand <= regfile_val;
+               end if;
+               if (dec_instr.saddr2 = reg_addr)  and  (dec_instr.op_detail(IMM_OPT) = '0') then
+                       right_operand <= regfile_val;
+               end if;
+       end if;
+end process forward;
+
+result <= reg.result;
+result_addr <= reg.res_addr;
+alu_jump <= reg.alu_jump;
+brpr <= reg.brpr;
+wr_en <= reg.wr_en;
+dmem <= alu_nxt.mem_op;
+--dmem <= reg.result(4);
+dmem_write_en <= alu_nxt.mem_en;
+--dmem_write_en <= reg.result(0);
+--dmem_write_en <= '1';
+hword <= alu_nxt.hw_op;
+--hword <= reg.result(1);
+byte_s <= alu_nxt.byte_op;
+--byte_s <= reg.result(2);
 end behav;