kleine Änderungen

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 080fb00accba7186704cd9e474927f4c8c5a4beb..73c7bf27e638d8cc0a063306cf22117f82f80d5f 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.alu_pkg.all;
+use work.gpm_pkg.all;
 
 architecture behav of execute_stage is
 
@@ -28,14 +29,18 @@ begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-        op_detail, left_operand, right_operand, alu_state, alu_nxt,addr,data);
+         left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data);
+
+gpm_inst : gpm
+        generic map(RESET_VALUE)
+        port map(clk,reset,alu_nxt,psw);
 
 syn: process(clk, reset)
 
 begin
 
        if reset = RESET_VALUE then
-               reg.alu_jmp <= '0';
+               reg.alu_jump <= '0';
                 reg.brpr <= '0';
                 reg.wr_en <= '0';
                 reg.result <= (others =>'0');
@@ -46,14 +51,13 @@ begin
        
 end process;
 
-asyn: process(reset,dec_instr, alu_nxt, psw)
+asyn: process(reset,dec_instr, alu_nxt, psw, reg,left_operand,right_operand)
 begin
 
         condition <= dec_instr.condition;
         op_group <= dec_instr.op_group;
         op_detail <= dec_instr.op_detail;
-        left_operand <= dec_instr.src1;
-        right_operand <= dec_instr.src2;
+        
 
 
         alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0'); 
@@ -69,19 +73,38 @@ begin
         reg_nxt.alu_jump <= alu_nxt.alu_jump;
         reg_nxt.wr_en <= alu_nxt.reg_op;
         reg_nxt.result <= alu_nxt.result;
-        reg_nxt.reg_addr <= alu_nxt.result_addr;
+        reg_nxt.res_addr <= alu_nxt.result_addr;
 
 end process asyn;
 
+forward: process(regfile_val, reg_we, reg_addr, dec_instr)
+begin
+       left_operand <= dec_instr.src1;
+        right_operand <= dec_instr.src2;
+
+       if reg_we = '1' then
+               if dec_instr.saddr1 = reg_addr then
+                       left_operand <= regfile_val;
+               end if;
+               if (dec_instr.saddr2 = reg_addr)  and  (dec_instr.op_detail(IMM_OPT) = '0') then
+                       right_operand <= regfile_val;
+               end if;
+       end if;
+end process forward;
+
 result <= reg.result;
 result_addr <= reg.res_addr;
-alu_jmp <= reg.alu_jump;
-brbr <= reg.brpr;
+alu_jump <= reg.alu_jump;
+brpr <= reg.brpr;
 wr_en <= reg.wr_en;
 dmem <= alu_nxt.mem_op;
+--dmem <= reg.result(4);
 dmem_write_en <= alu_nxt.mem_en;
+--dmem_write_en <= reg.result(0);
+--dmem_write_en <= '1';
 hword <= alu_nxt.hw_op;
+--hword <= reg.result(1);
 byte_s <= alu_nxt.byte_op;
-
+--byte_s <= reg.result(2);
 end behav;