use work.common_pkg.all;
use work.alu_pkg.all;
-use work.gpm_pkg.all;
+--use work.gpm_pkg.all;
+use work.extension_pkg.all;
architecture behav of execute_stage is
signal left_operand, right_operand : gp_register_t;
signal alu_state, alu_nxt : alu_result_rec;
signal psw : status_rec;
+ -- extension signals
+ signal ext_gpmp : extmod_rec;
+ signal data_out : gp_register_t;
+
+signal pval, pval_nxt : gp_register_t;
+signal paddr : paddr_t;
+signal pinc, pwr_en : std_logic;
+
+
type exec_internal is record
result : gp_register_t;
alu_inst : alu
port map(clk, reset, condition, op_group,
- left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data);
+ left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, pval_nxt, alu_nxt,addr,data, pinc, pwr_en, paddr);
+
+
+
+ gpmp_inst : extension_gpm
+ generic map (RESET_VALUE)
+ port map (
+ clk,
+ reset,
+ ext_gpmp,
+ ext_data_out,
+ alu_nxt.status,
+ paddr,
+ pinc,
+ pwr_en,
+ psw,
+ pval,
+ pval_nxt
+ );
+
-gpm_inst : gpm
- generic map(RESET_VALUE)
- port map(clk,reset,alu_nxt,psw);
syn: process(clk, reset)
- alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0');
+ alu_state <= (reg.result,dec_instr.daddr,psw,reg.alu_jump,reg.brpr,'0','0','0','0','0','0');
if reset = RESET_VALUE then
alu_jump <= reg.alu_jump;
brpr <= reg.brpr;
wr_en <= reg.wr_en;
+
dmem <= alu_nxt.mem_op;
+
--dmem <= reg.result(4);
+
dmem_write_en <= alu_nxt.mem_en;
+
--dmem_write_en <= reg.result(0);
--dmem_write_en <= '1';
+
hword <= alu_nxt.hw_op;
+
--hword <= reg.result(1);
+
byte_s <= alu_nxt.byte_op;
+
+--addr <= alu_nxt.result;
+--data <= right_operand;
--byte_s <= reg.result(2);
end behav;