dt: baudrate an PLL (50MHz) angepasst

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index f2c2dc2a98341f59583b3fe81d138e1bf66b8d98..1c4a6bcaa630ff181bcf77acf3db66a285d00605 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -19,7 +19,7 @@ signal psw : status_rec;
                signal ext_gpmp :  extmod_rec;
                signal data_out    : gp_register_t;
 
-signal pval : gp_register_t;
+signal pval, pval_nxt : gp_register_t;
 signal paddr : paddr_t;
 signal pinc, pwr_en : std_logic;
 
@@ -39,7 +39,7 @@ begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-         left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, alu_nxt,addr,data, pinc, pwr_en, paddr);
+         left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, pval_nxt, alu_nxt,addr,data, pinc, pwr_en, paddr);
 
 
 
@@ -55,7 +55,8 @@ port map(clk, reset, condition, op_group,
                        pinc,
                        pwr_en,
                        psw,
-                       pval
+                       pval,
+                       pval_nxt
                );
 
 
@@ -122,13 +123,20 @@ result_addr <= reg.res_addr;
 alu_jump <= reg.alu_jump;
 brpr <= reg.brpr;
 wr_en <= reg.wr_en;
+
 dmem <= alu_nxt.mem_op;
+
 --dmem <= reg.result(4);
+
 dmem_write_en <= alu_nxt.mem_en;
+
 --dmem_write_en <= reg.result(0);
 --dmem_write_en <= '1';
+
 hword <= alu_nxt.hw_op;
+
 --hword <= reg.result(1);
+
 byte_s <= alu_nxt.byte_op;
 
 --addr <= alu_nxt.result;