dt: baudrate an PLL (50MHz) angepasst

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index a8d3bde57bfbc280729be3cd777bf3733779c9bf..531ccd1b43f9b6027076d9aaedbb58b5ff699ed7 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -174,7 +174,7 @@ begin
 --
 
                        writeback_st : writeback_stage
-                generic map('0', '1', "altera", 2083)
+                generic map('0', '1', "altera", 5208)
                 port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,

diff --git a/dt/dt.qpf b/dt/dt.qpf
index f311d835db62242dda23749d5cd87ea6880958be..6785b58095be542b4b216b206b8e886df7413163 100644 (file)
--- a/dt/dt.qpf
+++ b/dt/dt.qpf
@@ -18,14 +18,14 @@
 #
 # Quartus II
 # Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-# Date created = 15:17:41  January 19, 2011
+# Date created = 11:39:04  January 20, 2011
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "10.0"
-DATE = "15:17:41  January 19, 2011"
+DATE = "11:39:04  January 20, 2011"
 
 # Revisions
 
-PROJECT_REVISION = "DSE"
 PROJECT_REVISION = "dt"
+PROJECT_REVISION = "DSE"

diff --git a/dt/dt.qsf b/dt/dt.qsf
index 4f558f7e8bf529bb478fa92f7c6ea14797ef5b3c..813526896b46f3fa9a18f8716c846e514204f78b 100644 (file)
--- a/dt/dt.qsf
+++ b/dt/dt.qsf
@@ -81,7 +81,6 @@ set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
 
 
 
-set_global_assignment -name VHDL_FILE ../cpu/src/core_top_c2de1.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd
@@ -101,7 +100,6 @@ set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd
-set_global_assignment -name VHDL_FILE ../cpu/src/pipeline_tb.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd
 set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd
@@ -143,4 +141,5 @@ set_global_assignment -name MISC_FILE /homes/c0725782/calu/dt/dt.dpf
 
 set_global_assignment -name VHDL_FILE pll/pll.vhd
 set_location_assignment PIN_152 -to sys_clk_in
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file