kleine Änderungen

[calu.git] / cpu / src / decode_stage_b.vhd

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index fbaf0101d7804730f7ff60632e9fdae7f44dc765..14846b227dc9cf202181500064fa0dc3c5049968 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -57,8 +57,9 @@ begin
                rtw_rec.immediate <= (others => '0');
                rtw_rec.imm_set <= '0';
 
-               dec_op_inst.condition <= (others => '0');
+               dec_op_inst.condition <= (others => '1');
                dec_op_inst.op_detail <= (others => '0');
+               dec_op_inst.op_group <= ADDSUB_OP;
                dec_op_inst.brpr <= '0'; --branch_prediction_bit;
                dec_op_inst.src1 <= (others => '0');
                dec_op_inst.src2 <= (others => '0');
@@ -113,21 +114,22 @@ begin
        dec_op_inst_nxt.src2 <= (others => '0');
        dec_op_inst_nxt.saddr1 <= instr_spl.reg_src1_addr;
        dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
-       dec_op_inst_nxt.daddr <= (others => '0');
+       dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0');
+       dec_op_inst_nxt.op_group <= instr_spl.op_group;
 
 end process;
 
 -- async process: decides between memory and read-through-write buffer on output
-output: process(rtw_rec, reg1_mem_data, reg2_mem_data)
+output: process(rtw_rec, rtw_rec_nxt, reg1_mem_data, reg2_mem_data)
 
 begin
-       if (rtw_rec.rtw_reg1 = '1') then
+       if ((rtw_rec.rtw_reg1) = '1') then
                reg1_rd_data <= rtw_rec.rtw_reg;
        else
                reg1_rd_data <= reg1_mem_data;
        end if;
 
-       if (rtw_rec.rtw_reg2 = '1') then
+       if ((rtw_rec.rtw_reg2) = '1') then
                reg2_rd_data <= rtw_rec.rtw_reg;
        else
                reg2_rd_data <= reg2_mem_data;
@@ -136,6 +138,7 @@ begin
        if (rtw_rec.imm_set = '1') then
                reg2_rd_data <= rtw_rec.immediate;
        end if;
+
 end process;
 
 
@@ -149,6 +152,8 @@ begin
        rtw_rec_nxt.rtw_reg2 <= '0';
        rtw_rec_nxt.immediate <= (others => '0');
        rtw_rec_nxt.imm_set <= '0';
+       rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
+       rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
 
        if (instr_spl.op_detail(IMM_OPT) = '1') then
                rtw_rec_nxt.immediate <= instr_spl.immediate;