use work.common_pkg.all;
use work.core_pkg.all;
+use work.extension_pkg.all;
entity core_top is
port(
--System input pins
+ sys_res : in std_logic;
sys_clk : in std_logic;
- sys_res : in std_logic;
- result : out gp_register_t
-
+-- result : out gp_register_t;
+-- reg_wr_data : out gp_register_t
+ -- uart
+ bus_tx : out std_logic
);
end core_top;
architecture behav of core_top is
+ signal jump_result : instruction_addr_t;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
signal branch_prediction_bit_pin : std_logic;
signal alu_jump_bit_pin : std_logic;
signal instruction_pin : instruction_word_t;
+ signal prog_cnt_pin : instruction_addr_t;
signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
signal reg_wr_data_pin : gp_register_t;
signal dmem_wr_en_pin : std_logic;
signal hword_pin : std_logic;
signal byte_s_pin : std_logic;
+
+ signal gpm_in_pin : extmod_rec;
+ signal gpm_out_pin : gp_register_t;
+ signal nop_pin : std_logic;
begin
alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
--Data outputs
- instruction => instruction_pin --: out instruction_word_t
+ instruction => instruction_pin, --: out instruction_word_t
+ prog_cnt => prog_cnt_pin
);
decode_st : decode_stage
--Data inputs
instruction => instruction_pin, --: in instruction_word_t;
+ prog_cnt => prog_cnt_pin,
reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
reg_we => reg_we_pin, --: in std_logic;
+ nop => nop_pin,
--Data outputs
branch_prediction_res => prediction_result_pin, --: instruction_word_t;
exec_st : execute_stage
generic map('0')
- port map(sys_clk, sys_res,to_next_stage, result_pin, result_addr_pin,addr_pin,
- data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
+ port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+ data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
writeback_st : writeback_stage
generic map('0', '1')
port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx);
+
+
+
--init : process(all)
--end process;
- result <= result_pin;
+-- result <= result_pin;
+ nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
+
+ jump_result <= prog_cnt_pin; --jump_result_pin;
+-- sys_res <= '1';
+-- reg_wr_data <= reg_wr_data_pin;
end behav;