nop insertion added

[calu.git] / cpu / src / core_pkg.vhd

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 301a51792296413b233f0e39bb65b8f08d1af2e3..b613dcba1ea7f9e954a73d8d7592e75a9b49c337 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -12,7 +12,7 @@ package core_pkg is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
@@ -39,30 +39,68 @@ package core_pkg is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+
+               --Data inputs
+                       instruction : in instruction_word_t;
+                       reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+                       reg_wr_data : in gp_register_t;
+                       reg_we : in std_logic;
+                       nop : in std_logic;
+
+               --Data outputs
+--                     reg1_rd_data : out gp_register_t;
+--                     reg2_rd_data : out gp_register_t;
+                       branch_prediction_res : out instruction_word_t;
+                       branch_prediction_bit : out std_logic;
+                       to_next_stage : out dec_op
                );
        end component decode_stage;
 
 
+       component decoder is
+
+       port(
+                       instruction : in instruction_word_t;
+                       instr_spl : out instruction_rec
+               
+               );
+
+       end component decoder;
 
        component execute_stage is
+       
        generic (
                        -- active reset value
-                       RESET_VALUE : std_logic;
+                       RESET_VALUE : std_logic
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       --LOGIC_ACT : std_logic;
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+                        dec_instr : in dec_op;
+
+                --System output
+                        result : out gp_register_t;--reg
+                        result_addr : out gp_addr_t;--reg
+                        addr : out word_t; --memaddr
+                        data : out gp_register_t; --mem data --ureg
+                        alu_jump : out std_logic;--reg
+                        brpr  : out std_logic;  --reg
+                        wr_en : out std_logic;--regop --reg
+                        dmem  : out std_logic;--memop
+                        dmem_write_en : out std_logic;
+                        hword  : out std_logic;
+                        byte_s : out std_logic
                );
        end component execute_stage;
 
@@ -73,15 +111,34 @@ package core_pkg is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+
+                       result : in gp_register_t;      --reg  (alu result or jumpaddr)
+                       result_addr : in gp_addr_t;     --reg
+                       address : in word_t;            --ureg 
+                       ram_data : in word_t;           --ureg
+                       alu_jmp : in std_logic;         --reg
+                       br_pred : in std_logic;         --reg
+                       write_en : in std_logic;        --reg  (register file)
+                       dmem_en : in std_logic;         --ureg (jump addr in mem or in address)
+                       dmem_write_en : in std_logic;   --ureg
+                       hword : in std_logic;           --ureg
+                       byte_s : in std_logic;          --ureg  
+
+                       regfile_val : out gp_register_t;
+                       reg_we : out std_logic;
+                       reg_addr : out gp_addr_t;
+                       jump_addr : out instruction_addr_t;
+                       jump : out std_logic
                );
        end component writeback_stage;
 
 
+
 end package core_pkg;