muh

[calu.git] / cpu / src / core_pkg.vhd

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index bc45ecdf0aa408c577e33eb6976bba783572be13..b243fbabeaae7f3a54172386be36a40aa47b9c71 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -20,6 +20,7 @@ package core_pkg is
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+                       s_reset : in std_logic;
                
                --Data inputs
                        jump_result : in instruction_addr_t;
@@ -126,7 +127,8 @@ package core_pkg is
                        RESET_VALUE : std_logic;
                        -- active logic value
                        LOGIC_ACT : std_logic;
-                       FPGATYPE : string
+                       FPGATYPE : string;
+                       CLK_BAUD : integer
                        );
        port(
                --System inputs
@@ -162,8 +164,15 @@ package core_pkg is
                        sseg2 : out std_logic_vector(0 to 6);
                        sseg3 : out std_logic_vector(0 to 6);
 
-                       int_req : out interrupt_t
-
+                       int_req : out interrupt_t;
+                       
+                       LCD_DATA_8 : out std_logic_vector(7 downto 0);
+                       LCD_BLON : out std_logic;
+                       LCD_RW : out std_logic;
+                       LCD_EN : out std_logic;
+                       LCD_RS : out std_logic;
+                       LCD_ON : out std_logic;
+                       lcd_data : out std_logic_vector(6 downto 0)
                );
        end component writeback_stage;