RESET_VALUE : std_logic;
-- active logic value
LOGIC_ACT : std_logic;
- FPGATYPE : string
+ FPGATYPE : string;
+ CLK_BAUD : integer
);
port(
--System inputs
sseg2 : out std_logic_vector(0 to 6);
sseg3 : out std_logic_vector(0 to 6);
- int_req : out interrupt_t
-
+ int_req : out interrupt_t;
+
+ LCD_DATA_8 : out std_logic_vector(7 downto 0);
+ LCD_BLON : out std_logic;
+ LCD_RW : out std_logic;
+ LCD_EN : out std_logic;
+ LCD_RS : out std_logic;
+ LCD_ON : out std_logic;
+ lcd_data : out std_logic_vector(6 downto 0)
);
end component writeback_stage;