uart und extension anbindung

[calu.git] / cpu / src / core_pkg.vhd

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 4d318708cdfd760e055dd5c922bac765ca92ca2a..afd50b666d4153702c1f1c91d54257f3606a4a8c 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -4,6 +4,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
+use work.extension_pkg.all;
 
 package core_pkg is
        
@@ -142,7 +143,15 @@ package core_pkg is
                        reg_we : out std_logic;
                        reg_addr : out gp_addr_t;
                        jump_addr : out instruction_addr_t;
-                       jump : out std_logic
+                       jump : out std_logic;
+                       -- same here
+                       bus_tx : out std_logic;
+                       bus_rx : in std_logic;
+                       
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6)
                );
        end component writeback_stage;