uart und extension anbindung

[calu.git] / cpu / src / core_pkg.vhd

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 0072827490c593cda242776e3ada5b1acd0e565c..afd50b666d4153702c1f1c91d54257f3606a4a8c 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -145,7 +145,13 @@ package core_pkg is
                        jump_addr : out instruction_addr_t;
                        jump : out std_logic;
                        -- same here
-                       bus_tx : out std_logic
+                       bus_tx : out std_logic;
+                       bus_rx : in std_logic;
+                       
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6)
                );
        end component writeback_stage;