bugfix: sp operation first approach.

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 3fb3434827af3647c95b48f6a2770de187f20901..b0bf5a4419d68a60f2014a75e741bfc55ce399d4 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -22,35 +22,53 @@ architecture behaviour of alu is
        end component exec_op;\r
        \r
        signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
+        signal left_o, right_o : gp_register_t;\r
        \r
 begin\r
 \r
-       add_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result);\r
+       add_inst : entity work.exec_op(add_op)\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result);\r
        \r
-       and_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result);\r
-       or_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result);\r
-       xor_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result);\r
+       and_inst : entity work.exec_op(and_op)\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);\r
+\r
+       or_inst : entity work.exec_op(or_op)\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);\r
+\r
+       xor_inst : entity work.exec_op(xor_op)\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);\r
        \r
-       shift_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);\r
+       shift_inst : entity work.exec_op(shift_op)\r
+       port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);\r
 \r
-calc: process(cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval)\r
        variable result_v : alu_result_rec;\r
        variable res_prod : std_logic;\r
        variable cond_met : std_logic;\r
        variable mem_en : std_logic;\r
+        variable mem_op : std_logic;\r
+       variable alu_jump : std_logic;\r
+       variable nop     : std_logic;\r
 begin\r
        result_v := alu_state;\r
        \r
-       result_v.result := add_result.result;\r
        res_prod := '1';\r
-       mem_en := '0';
+       mem_en := '0';\r
+    mem_op := '0';\r
+       alu_jump := '0';\r
+  \r
+        left_o <= left_operand;\r
+        right_o <= right_operand;\r
+\r
         addr <= add_result.result;\r
+        data <= right_operand;\r
        \r
+       pinc <= '0';\r
+       pwr_en <= '0';\r
+       paddr <= (others =>'0');\r
+       \r
+       result_v.result := add_result.result;\r
+\r
        case cond is\r
        when COND_NZERO =>\r
                cond_met := not(alu_state.status.zero);\r
@@ -83,10 +101,13 @@ begin
        when COND_ALWAYS =>\r
                cond_met := '1';\r
        when COND_NEVER =>\r
-               cond_met := '0';
+               cond_met := '0';\r
        when others => null;\r
        end case;\r
        \r
+       nop := (alu_state.alu_jump xnor alu_state.brpr);\r
+       cond_met := cond_met and nop;\r
+\r
        case op_group is\r
        when ADDSUB_OP =>\r
                result_v := add_result;\r
@@ -98,8 +119,29 @@ begin
                result_v := xor_result;\r
        when SHIFT_OP =>\r
                result_v := shift_result;\r
+        when LDST_OP =>\r
+                res_prod := '0';\r
+                mem_op := '1';\r
+                if op_detail(IMM_OPT) = '1' then\r
+                        result_v.result := right_operand;\r
+                        res_prod := '1';\r
+                        mem_op := '0';\r
+                end if;\r
+                if op_detail(ST_OPT) = '1' then\r
+                        right_o <= displacement;\r
+                        mem_en := '1';\r
+                end if;\r
+       when JMP_OP =>\r
+               if op_detail(JMP_REG_OPT) = '0' then\r
+                       left_o <= prog_cnt;\r
+               end if;\r
+               alu_jump := '1';\r
+       when JMP_ST_OP => null;\r
+               \r
        end case;\r
        \r
+\r
+       result_v.status.zero := '0';\r
        if result_v.result = REG_ZERO then\r
                result_v.status.zero := '1';\r
        end if;\r
@@ -111,34 +153,20 @@ begin
        end if;\r
        \r
        result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
-       result_v.mem_en := mem_en and cond_met;
-
+       result_v.mem_en := mem_en and cond_met;\r
+    result_v.mem_op := mem_op and cond_met;\r
+       result_v.alu_jump := alu_jump and cond_met;\r
+       result_v.brpr := brpr and nop;\r
         \r
-       data <= add_result.result;\r
+       if (result_v.alu_jump = '0') and (brpr = '1') then\r
+               result_v.result := (others => '0');\r
+               result_v.result(prog_cnt'range) := std_logic_vector(unsigned(prog_cnt)+1);\r
+               --result_v.reg_op := '1';\r
+       end if;\r
+\r
        alu_result <= result_v;\r
        \r
 end process calc; \r
 \r
 end architecture behaviour;\r
 \r
-configuration alu_cfg of alu is\r
-\r
-       for behaviour\r
-               for add_inst : exec_op \r
-                       use entity work.exec_op(add_op);\r
-               end for;\r
-               for and_inst : exec_op \r
-                       use entity work.exec_op(and_op);\r
-               end for;\r
-               for or_inst : exec_op\r
-                       use entity work.exec_op(or_op);\r
-               end for;\r
-               for xor_inst : exec_op\r
-                       use entity work.exec_op(xor_op);\r
-               end for;\r
-               for shift_inst : exec_op\r
-                       use entity work.exec_op(shift_op);\r
-               end for;\r
-       end for;\r
-               \r
-end configuration alu_cfg;\r