Added missing signals to sensitivity and extended writeback

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index de8980d67866bc865dac894842392ba651093736..9a0749155f5c5070eacfb780f779a2516fb67f29 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -41,7 +41,7 @@ begin
        shift_inst : entity work.exec_op(shift_op)\r
        port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);\r
 \r
-calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval, pval_nxt)\r
        variable result_v : alu_result_rec;\r
        variable res_prod : std_logic;\r
        variable cond_met : std_logic;\r
@@ -127,13 +127,14 @@ begin
         when LDST_OP =>\r
                 res_prod := '0';\r
                 mem_op := '1';\r
+               --right_o <= displacement;\r
+               addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));\r
                 if op_detail(IMM_OPT) = '1' then\r
                         result_v.result := right_operand;\r
                         res_prod := '1';\r
                         mem_op := '0';\r
                 end if;\r
                 if op_detail(ST_OPT) = '1' then\r
-                        right_o <= displacement;\r
                         mem_en := '1';\r
                 end if;\r
        when JMP_OP =>\r
@@ -152,9 +153,12 @@ begin
                \r
                addr <= pval;\r
                data <= prog_cnt_nxt;\r
-               -- if(op_detail(RET_OPT) = '1' then\r
-                       -- null;\r
-               -- end if;\r
+               if op_detail(RET_OPT) = '1' then\r
+                       addr <= pval_nxt;\r
+                       mem_en := '0';\r
+                       pinc_v := '0';\r
+                       res_prod := '0';\r
+               end if;\r
                \r
        end case;\r
        \r
@@ -184,6 +188,9 @@ begin
                --result_v.reg_op := '1';\r
        end if;\r
 \r
+       -- if result_v.mem_op = '0' then --- do this if selecting enable for extension modules is too slow.\r
+               -- addr <= (others => '0');\r
+       -- end if;\r
        alu_result <= result_v;\r
        pinc <= pinc_v;\r
        pwr_en <= pwr_en_v;\r