Added missing signals to sensitivity and extended writeback

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index c0bfbb2b58e36f1dd47d09d10be4eda5ca809ea9..9a0749155f5c5070eacfb780f779a2516fb67f29 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -127,7 +127,8 @@ begin
         when LDST_OP =>\r
                 res_prod := '0';\r
                 mem_op := '1';\r
-                               right_o <= displacement;\r
+               --right_o <= displacement;\r
+               addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));\r
                 if op_detail(IMM_OPT) = '1' then\r
                         result_v.result := right_operand;\r
                         res_prod := '1';\r
@@ -187,6 +188,9 @@ begin
                --result_v.reg_op := '1';\r
        end if;\r
 \r
+       -- if result_v.mem_op = '0' then --- do this if selecting enable for extension modules is too slow.\r
+               -- addr <= (others => '0');\r
+       -- end if;\r
        alu_result <= result_v;\r
        pinc <= pinc_v;\r
        pwr_en <= pwr_en_v;\r