); \r
end component exec_op;\r
\r
- signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
- signal left, right : gp_register_t;\r
+ signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
+ signal left_o, right_o : gp_register_t;\r
\r
begin\r
\r
add_inst : entity work.exec_op(add_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, add_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result);\r
\r
and_inst : entity work.exec_op(and_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, and_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);\r
\r
or_inst : entity work.exec_op(or_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, or_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);\r
\r
xor_inst : entity work.exec_op(xor_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, xor_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);\r
\r
shift_inst : entity work.exec_op(shift_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, shift_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);\r
\r
-calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval, pval_nxt)\r
variable result_v : alu_result_rec;\r
variable res_prod : std_logic;\r
variable cond_met : std_logic;\r
- variable mem_en : std_logic;
+ variable mem_en : std_logic;\r
variable mem_op : std_logic;\r
+ variable alu_jump : std_logic;\r
+ variable nop : std_logic;\r
+ \r
+ variable pinc_v, pwr_en_v : std_logic;\r
+ \r
+ variable prog_cnt_nxt : std_logic_vector(prog_cnt'range);\r
begin\r
result_v := alu_state;\r
\r
- result_v.result := add_result.result;\r
res_prod := '1';\r
- mem_en := '0';
- mem_op := '0';\r
- addr <= add_result.result;
- left <= left_operand;
- right <= right_operand;\r
+ mem_en := '0';\r
+ mem_op := '0';\r
+ alu_jump := '0';\r
+ \r
+ left_o <= left_operand;\r
+ right_o <= right_operand;\r
+\r
+ addr <= add_result.result;\r
+ data <= right_operand;\r
\r
+ pinc_v := '0';\r
+ pwr_en_v := '0';\r
+ \r
+ paddr <= (others =>'0');\r
+ \r
+ result_v.result := add_result.result;\r
+ prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);\r
case cond is\r
when COND_NZERO =>\r
cond_met := not(alu_state.status.zero);\r
when others => null;\r
end case;\r
\r
+ nop := (alu_state.alu_jump xnor alu_state.brpr);\r
+ cond_met := cond_met and nop;\r
+\r
case op_group is\r
when ADDSUB_OP =>\r
result_v := add_result;\r
when XOR_OP =>\r
result_v := xor_result;\r
when SHIFT_OP =>\r
- result_v := shift_result;
- when LDST_OP =>
- res_prod := '0';
- mem_op := '1';
- if op_detail(IMM_OPT) = '1' then
- result_v.result := right_operand;
- res_prod := '1';
- mem_op := '0';
- end if;
- if op_detail(ST_OPT) = '1' then
- right <= displacement;
- mem_en := '1';
+ result_v := shift_result;\r
+ when LDST_OP =>\r
+ res_prod := '0';\r
+ mem_op := '1';\r
+ --right_o <= displacement;\r
+ addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));\r
+ if op_detail(IMM_OPT) = '1' then\r
+ result_v.result := right_operand;\r
+ res_prod := '1';\r
+ mem_op := '0';\r
+ end if;\r
+ if op_detail(ST_OPT) = '1' then\r
+ mem_en := '1';\r
end if;\r
+ when JMP_OP =>\r
+ if op_detail(JMP_REG_OPT) = '0' then\r
+ left_o <= prog_cnt;\r
+ end if;\r
+ alu_jump := '1';\r
+ when JMP_ST_OP => \r
+ left_o <= prog_cnt;\r
+ mem_en := '1';\r
+ alu_jump := '1';\r
+ mem_op := '1';\r
+ pinc_v := '1';\r
+ pwr_en_v := '1';\r
+ paddr <= (others =>'0');\r
+ \r
+ addr <= pval;\r
+ data <= prog_cnt_nxt;\r
+ if op_detail(RET_OPT) = '1' then\r
+ addr <= pval_nxt;\r
+ mem_en := '0';\r
+ pinc_v := '0';\r
+ res_prod := '0';\r
+ end if;\r
+ \r
end case;\r
\r
\r
end if;\r
\r
result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
- result_v.mem_en := mem_en and cond_met;
- result_v.mem_op := mem_op and cond_met;\r
+ result_v.mem_en := mem_en and cond_met;\r
+ result_v.mem_op := mem_op and cond_met;\r
+ result_v.alu_jump := alu_jump and cond_met;\r
+ result_v.brpr := brpr and nop;\r
+ \r
+ pwr_en_v := pwr_en_v and cond_met;\r
+ \r
+ if (result_v.alu_jump = '0') and (brpr = '1') then\r
+ result_v.result := (others => '0');\r
+ result_v.result(prog_cnt'range) := prog_cnt_nxt;\r
+ --result_v.reg_op := '1';\r
+ end if;\r
\r
+ -- if result_v.mem_op = '0' then --- do this if selecting enable for extension modules is too slow.\r
+ -- addr <= (others => '0');\r
+ -- end if;\r
alu_result <= result_v;\r
+ pinc <= pinc_v;\r
+ pwr_en <= pwr_en_v;\r
\r
end process calc; \r
\r
projects / calu.git / blobdiff