ldi add finished

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 511b15426f36e640b167936aea137bc07290dd9c..634c7d1605504d5127b136c82c8828fc3fbcdb9a 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -25,20 +25,22 @@ architecture behaviour of alu is
        \r
 begin\r
 \r
-       add_inst : exec_op\r
+       add_inst : entity work.exec_op(add_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result);\r
        \r
-       and_inst : exec_op\r
+       and_inst : entity work.exec_op(and_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result);\r
-       or_inst : exec_op\r
+\r
+       or_inst : entity work.exec_op(or_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result);\r
-       xor_inst : exec_op\r
+\r
+       xor_inst : entity work.exec_op(xor_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result);\r
        \r
-       shift_inst : exec_op\r
+       shift_inst : entity work.exec_op(shift_op)\r
        port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);\r
 \r
-calc: process(condition, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+calc: process(left_operand, right_operand, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
        variable result_v : alu_result_rec;\r
        variable res_prod : std_logic;\r
        variable cond_met : std_logic;\r
@@ -49,8 +51,9 @@ begin
        result_v.result := add_result.result;\r
        res_prod := '1';\r
        mem_en := '0';\r
+        addr <= add_result.result;\r
        \r
-       case condition is\r
+       case cond is\r
        when COND_NZERO =>\r
                cond_met := not(alu_state.status.zero);\r
        when COND_ZERO =>\r
@@ -83,6 +86,7 @@ begin
                cond_met := '1';\r
        when COND_NEVER =>\r
                cond_met := '0';\r
+       when others => null;\r
        end case;\r
        \r
        case op_group is\r
@@ -95,9 +99,15 @@ begin
        when XOR_OP =>\r
                result_v := xor_result;\r
        when SHIFT_OP =>\r
-               result_v := shift_result;\r
+               result_v := shift_result;
+        when LDST_OP =>
+                if op_detail(IMM_OPT) = '1' then
+                        result_v.result := right_operand;
+                end if;\r
        end case;\r
        \r
+\r
+       result_v.status.zero := '0';\r
        if result_v.result = REG_ZERO then\r
                result_v.status.zero := '1';\r
        end if;\r
@@ -108,33 +118,14 @@ begin
                result_v.status := alu_state.status;\r
        end if;\r
        \r
-       result_v.new_val := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
+       result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
        result_v.mem_en := mem_en and cond_met;\r
-       \r
+\r
+        \r
+       data <= add_result.result;\r
        alu_result <= result_v;\r
        \r
 end process calc; \r
 \r
 end architecture behaviour;\r
 \r
-configuration alu_cfg of alu is\r
-\r
-       for behaviour\r
-               for add_inst : exec_op \r
-                       use entity work.exec_op(add_op);\r
-               end for;\r
-               for and_inst : exec_op \r
-                       use entity work.exec_op(and_op);\r
-               end for;\r
-               for or_inst : exec_op\r
-                       use entity work.exec_op(or_op);\r
-               end for;\r
-               for xor_inst : exec_op\r
-                       use entity work.exec_op(xor_op);\r
-               end for;\r
-               for shift_inst : exec_op\r
-                       use entity work.exec_op(shift_op);\r
-               end for;\r
-       end for;\r
-               \r
-end configuration alu_cfg;\r