uart und extension anbindung

[calu.git] / cpu / sim / testcore.do

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index da92a48b390eaa2b7cc894f55eb8d925ef31251c..a52d799045dbf306a9cffae9a84da3ee2ae141e6 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -6,14 +6,57 @@ vcom -work work ../src/r_w_ram.vhd
 vcom -work work ../src/r_w_ram_b.vhd
 vcom -work work ../src/r2_w_ram.vhd
 vcom -work work ../src/r2_w_ram_b.vhd
+vcom -work work ../src/rom.vhd
+vcom -work work ../src/rom_b.vhd
+vcom -work work ../src/extension_pkg.vhd
 vcom -work work ../src/common_pkg.vhd
 vcom -work work ../src/core_pkg.vhd
+vcom -work work ../src/extension_uart_pkg.vhd
+vcom -work work ../src/extension_uart.vhd
+vcom -work work ../src/extension_uart_b.vhd
+vcom -work work ../src/extension_7seg_pkg.vhd
+vcom -work work ../src/extension_7seg.vhd
+vcom -work work ../src/extension_7seg_b.vhd
+vcom -work work ../src/rs232_tx.vhd
+vcom -work work ../src/rs232_tx_arc.vhd
+vcom -work work ../src/rs232_rx.vhd
+vcom -work work ../src/rs232_rx_arc.vhd
+
 vcom -work work ../src/decoder.vhd
 vcom -work work ../src/decoder_b.vhd
 vcom -work work ../src/fetch_stage.vhd
 vcom -work work ../src/fetch_stage_b.vhd
 vcom -work work ../src/decode_stage.vhd
 vcom -work work ../src/decode_stage_b.vhd
+
+vcom -work work ../src/alu_pkg.vhd
+vcom -work work ../src/extension_pkg.vhd
+
+vcom -work work ../src/exec_op.vhd
+vcom -work work ../src/exec_op/add_op_b.vhd
+vcom -work work ../src/exec_op/and_op_b.vhd
+vcom -work work ../src/exec_op/or_op_b.vhd
+vcom -work work ../src/exec_op/xor_op_b.vhd
+vcom -work work ../src/exec_op/shift_op_b.vhd
+
+vcom -work work ../src/alu.vhd
+vcom -work work ../src/alu_b.vhd
+vcom -work work ../src/extension_pkg.vhd
+#vcom -work work ../src/gpm_pkg.vhd
+
+#vcom -work work ../src/gpm.vhd
+#vcom -work work ../src/gpm_b.vhd
+
+vcom -work work ../src/extension.vhd
+vcom -work work ../src/extension_b.vhd
+
+vcom -work work ../src/execute_stage.vhd
+vcom -work work ../src/execute_stage_b.vhd
+
+
+vcom -work work ../src/writeback_stage.vhd
+vcom -work work ../src/writeback_stage_b.vhd
+
 vcom -work work ../src/pipeline_tb.vhd
 
 vsim work.pipeline_conf_beh -t ns
@@ -30,9 +73,24 @@ add wave  -radix hexadecimal /pipeline_tb/decode_st/instr_spl
 add wave  -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
+add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec_nxt
 add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_we
 
-run 500000 ns
+add wave  -radix hexadecimal /pipeline_tb/exec_st/gpmp_inst/psw
+
+add wave  -radix hexadecimal /pipeline_tb/addr_pin
+add wave  -radix hexadecimal /pipeline_tb/data_pin
+add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
+add wave  -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
+add wave  -radix hexadecimal /pipeline_tb/writeback_st/dmem_we
+add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_addr
+
+add wave  -radix hexadecimal /pipeline_tb/tx_pin
+add wave  -radix hexadecimal /pipeline_tb/rx_pin
+
+add wave  -radix decimal     /pipeline_tb/cycle_cnt
+
+run 10000 ns