uart und extension anbindung

[calu.git] / cpu / sim / testcore.do

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index 9a4c3fe0a01afc76ddc63d3c50b059284f037fd0..a52d799045dbf306a9cffae9a84da3ee2ae141e6 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -6,17 +6,22 @@ vcom -work work ../src/r_w_ram.vhd
 vcom -work work ../src/r_w_ram_b.vhd
 vcom -work work ../src/r2_w_ram.vhd
 vcom -work work ../src/r2_w_ram_b.vhd
-vcom -work work ../src/common_pkg.vhd
+vcom -work work ../src/rom.vhd
+vcom -work work ../src/rom_b.vhd
 vcom -work work ../src/extension_pkg.vhd
+vcom -work work ../src/common_pkg.vhd
+vcom -work work ../src/core_pkg.vhd
 vcom -work work ../src/extension_uart_pkg.vhd
 vcom -work work ../src/extension_uart.vhd
 vcom -work work ../src/extension_uart_b.vhd
+vcom -work work ../src/extension_7seg_pkg.vhd
+vcom -work work ../src/extension_7seg.vhd
+vcom -work work ../src/extension_7seg_b.vhd
 vcom -work work ../src/rs232_tx.vhd
 vcom -work work ../src/rs232_tx_arc.vhd
 vcom -work work ../src/rs232_rx.vhd
 vcom -work work ../src/rs232_rx_arc.vhd
 
-vcom -work work ../src/core_pkg.vhd
 vcom -work work ../src/decoder.vhd
 vcom -work work ../src/decoder_b.vhd
 vcom -work work ../src/fetch_stage.vhd
@@ -82,6 +87,10 @@ add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
 add wave  -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
 add wave  -radix hexadecimal /pipeline_tb/writeback_st/dmem_we
 add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_addr
+
+add wave  -radix hexadecimal /pipeline_tb/tx_pin
+add wave  -radix hexadecimal /pipeline_tb/rx_pin
+
 add wave  -radix decimal     /pipeline_tb/cycle_cnt
 
 run 10000 ns