Fixed some bugs.

[calu.git] / cpu / sim / testcore.do

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index da92a48b390eaa2b7cc894f55eb8d925ef31251c..6f5b7c880a0a78a5ce5892f088e2a64011c463c4 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -14,6 +14,31 @@ vcom -work work ../src/fetch_stage.vhd
 vcom -work work ../src/fetch_stage_b.vhd
 vcom -work work ../src/decode_stage.vhd
 vcom -work work ../src/decode_stage_b.vhd
+
+vcom -work work ../src/alu_pkg.vhd
+vcom -work work ../src/extension_pkg.vhd
+vcom -work work ../src/gpm_pkg.vhd
+
+vcom -work work ../src/exec_op.vhd
+vcom -work work ../src/exec_op/add_op_b.vhd
+vcom -work work ../src/exec_op/and_op_b.vhd
+vcom -work work ../src/exec_op/or_op_b.vhd
+vcom -work work ../src/exec_op/xor_op_b.vhd
+vcom -work work ../src/exec_op/shift_op_b.vhd
+
+vcom -work work ../src/alu.vhd
+vcom -work work ../src/alu_b.vhd
+
+vcom -work work ../src/gpm.vhd
+vcom -work work ../src/gpm_b.vhd
+
+vcom -work work ../src/execute_stage.vhd
+vcom -work work ../src/execute_stage_b.vhd
+
+
+vcom -work work ../src/writeback_stage.vhd
+vcom -work work ../src/writeback_stage_b.vhd
+
 vcom -work work ../src/pipeline_tb.vhd
 
 vsim work.pipeline_conf_beh -t ns