uart und extension anbindung

[calu.git] / cpu / create_project.tcl

diff --git a/cpu/create_project.tcl b/cpu/create_project.tcl
index 6419c5aaf07cb6e4dc181f757ff8fb42de4f9e00..367e4a27aa5d9cc8ac36da3975706459d7fb2b3b 100755 (executable)
--- a/cpu/create_project.tcl
+++ b/cpu/create_project.tcl
@@ -46,9 +46,85 @@ if {$make_assignments} {
        set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
        set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
        set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
+
+       set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd
+       set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd
+       set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd
+       set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd
+
+       set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
+
+       set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
+#      set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
+
+       set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd
+
+       set_global_assignment -name VHDL_FILE ../src/alu.vhd
+       set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
+
+#      set_global_assignment -name VHDL_FILE ../src/gpm.vhd
+#      set_global_assignment -name VHDL_FILE ../src/gpm_b.vhd
+
+       set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
+       set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
+
+
+       set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd
+       set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd
+
        
        set_location_assignment PIN_L1 -to sys_clk
        set_location_assignment PIN_R22 -to sys_res
+       set_location_assignment PIN_G12 -to bus_tx
+       set_location_assignment PIN_F14 -to bus_rx
+
+       set_location_assignment PIN_J2 -to sseg0[0]
+       set_location_assignment PIN_J1 -to sseg0[1]
+       set_location_assignment PIN_H2 -to sseg0[2]
+       set_location_assignment PIN_H1 -to sseg0[3]
+       set_location_assignment PIN_F2 -to sseg0[4]
+       set_location_assignment PIN_F1 -to sseg0[5]
+       set_location_assignment PIN_E2 -to sseg0[6]
+
+       set_location_assignment PIN_E1 -to sseg1[0]
+       set_location_assignment PIN_H6 -to sseg1[1]
+       set_location_assignment PIN_H5 -to sseg1[2]
+       set_location_assignment PIN_H4 -to sseg1[3]
+       set_location_assignment PIN_G3 -to sseg1[4]
+       set_location_assignment PIN_D2 -to sseg1[5]
+       set_location_assignment PIN_D1 -to sseg1[6]
+
+       set_location_assignment PIN_G5 -to sseg2[0]
+       set_location_assignment PIN_G6 -to sseg2[1]
+       set_location_assignment PIN_C2 -to sseg2[2]
+       set_location_assignment PIN_C1 -to sseg2[3]
+       set_location_assignment PIN_E3 -to sseg2[4]
+       set_location_assignment PIN_E4 -to sseg2[5]
+       set_location_assignment PIN_D3 -to sseg2[6]
+
+       set_location_assignment PIN_F4 -to sseg3[0]
+       set_location_assignment PIN_D5 -to sseg3[1]
+       set_location_assignment PIN_D6 -to sseg3[2]
+       set_location_assignment PIN_J4 -to sseg3[3]
+       set_location_assignment PIN_L8 -to sseg3[4]
+       set_location_assignment PIN_F3 -to sseg3[5]
+       set_location_assignment PIN_D4 -to sseg3[6]
+
 
        set_global_assignment -name FMAX_REQUIREMENT "80.00 MHz" -section_id sys_clk
        set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk