spartan3e: BRAM gehaxe. lesbarer und wird auch richtig(er) instanziert

[calu.git] / 3_test / uartint.s

diff --git a/3_test/uartint.s b/3_test/uartint.s
index bf8e43d46128840ef52b61b556a613c32cff487e..8afa8f23fa081bddfce80f9d4fd8f02e5c474166 100644 (file)
--- a/3_test/uartint.s
+++ b/3_test/uartint.s
@@ -1,65 +1,22 @@
 .text
 start:
        br+ main ;br+ 
-       call+ uartrdy ;call+ 0x80(128, 128)
+       br+ main
        ret
 main:
+       ldi r0, 0x2000 ; status...
        ldi r1, 0x200b ;ldi r1, 8203
        ldi r2, 0x200c ;ldi r2, 8204
-       ldi r3, 0x2010 ;ldi r3, 8208
-       ldi r4, 0x2024 ;ldi r4, 8228
-       ldi r5, 3
-       stw r5, 0(r4)
-       br+ start
-       ; stwnv r5, 0(r4)
-uartrdy:
-       ; load instructions into ram
-       ldi r8, 0x2037 ; paddr
-       ldi r9, 0x203b ; pdata
-
-    ; x"e7390000"; -- ldw r7, 0(r2)
-       xor r10, r10, r10
-       stw r10, 0(r8)
-       xor r10, r10, r10
-       ldi r10, 0xe739
-       lls r10, r10, 16
-       stw r10, 0(r9)
-
-       ;x"e7b98000"; -- stw r7, 0(r3)
-       xor r10, r10, r10
-       ldi r10, 1
-       stw r10, 0(r8)
-       xor r10, r10, r10
-       ldi r10, 0xe7b9
-       lls r10, r10, 8
-       addi r10, r10, 0x80
-       lls r10, r10, 8
-       stw r10, 0(r9)
-
-       ;x"e7b88000"; -- stw r7, 0(r1)
-       xor r10, r10, r10
-       ldi r10, 2
-       stw r10, 0(r8)
-       xor r10, r10, r10
-       ldi r10, 0xe7b8
-       lls r10, r10, 8
-       addi r10, r10, 0x80
-       lls r10, r10, 8
-       stw r10, 0(r9)
-
-       ;x"eb000008"; -- ret-
-       xor r10, r10, r10
-       ldi r10, 3
-       stw r10, 0(r8)
-       xor r10, r10, r10
-       ldi r10, 0xeb00
-       lls r10, r10, 16
-       addi r10, r10, 0x8
-       stw r10, 0(r9)
-       br hmm
-
-.org 0x1fc
-hmm:
-       ldinv r0, 0
-; real ram...
-woot:
+       ; ldi r4, 0x2024 ;ldi r4, 8228
+       ; ldi r5, 3 ; enable interrupts
+       ; stw r5, 0(r4)
+       ldw r5, 0(r0)
+       andx r5, 0x2
+       brzs+ main ; no new data?
+       ldw r7, 0(r2) ; load data
+uartnrdy:
+       ldw r5, 0(r0)
+       andx r5, 0x1
+       brnz+ uartnrdy ; transmitter not ready yet?
+       stw r7, 0(r1) ; send zeh shit!
+       br main ; back to usual stuff