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Rename almost all occurences of LinuxBIOS to coreboot.
[coreboot.git]
/
src
/
northbridge
/
amd
/
amdmct
/
mct
/
mctmtr_d.c
diff --git
a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index c0839d2a889f3c9abc0eb549bc1f4bbc54af2c75..d39bfcc8b26d4bdae5cd41d7099da01adabea3b7 100644
(file)
--- a/
src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/
src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@
-75,7
+75,7
@@
void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
Set default values for CPU registers
======================================================================*/
Set default values for CPU registers
======================================================================*/
- /* NOTE : For
LinuxBIOS
, we don't need to set mtrr enables here because
+ /* NOTE : For
coreboot
, we don't need to set mtrr enables here because
they are still enable from cache_as_ram.inc */
addr = 0x250;
they are still enable from cache_as_ram.inc */
addr = 0x250;
@@
-88,7
+88,7
@@
void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/*======================================================================
Set variable MTRR values
======================================================================*/
/*======================================================================
Set variable MTRR values
======================================================================*/
- /* NOTE: for
LinuxBIOS change from 0x200 to 0x204: LinuxBIOS
is using
+ /* NOTE: for
coreboot change from 0x200 to 0x204: coreboot
is using
0x200, 0x201 for [1M, CONFIG_TOP_MEM)
0x202, 0x203 for ROM Caching
*/
0x200, 0x201 for [1M, CONFIG_TOP_MEM)
0x202, 0x203 for ROM Caching
*/