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Rename almost all occurences of LinuxBIOS to coreboot.
[coreboot.git]
/
src
/
mainboard
/
tyan
/
s2880
/
Options.lb
diff --git
a/src/mainboard/tyan/s2880/Options.lb
b/src/mainboard/tyan/s2880/Options.lb
index a6b4e86f508604b204a65eeb471023faf5f32da4..72c40d9466cd2cf2a3de0efd2de09ba66c9e995a 100644
(file)
--- a/
src/mainboard/tyan/s2880/Options.lb
+++ b/
src/mainboard/tyan/s2880/Options.lb
@@
-3,9
+3,6
@@
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
@@
-19,8
+16,10
@@
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
@@
-36,7
+35,7
@@
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses
LINUXBIOS
_EXTRA_VERSION
+uses
COREBOOT
_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
@@
-47,6
+46,7
@@
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses CROSS_COMPILE
uses CC
uses HOSTCC
@@
-54,8
+54,11
@@
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
-uses
K8_E0
_MEM_HOLE_SIZEK
+uses
HW
_MEM_HOLE_SIZEK
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
###
uses CONFIG_USE_INIT
###
@@
-70,7
+73,9
@@
default ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
##
## Build code for the fallback boot
##
## Build code for the fallback boot
@@
-78,17
+83,10
@@
default FALLBACK_SIZE=131072
default HAVE_FALLBACK_BOOT=1
##
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from
linuxBIOS
+## Build code to reset the motherboard from
coreboot
##
default HAVE_HARD_RESET=1
##
default HAVE_HARD_RESET=1
-##
-## Funky hard reset implementation
-##
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
##
## Build code to export a programmable irq routing table
##
##
## Build code to export a programmable irq routing table
##
@@
-107,7
+105,7
@@
default HAVE_MP_TABLE=1
default HAVE_OPTION_TABLE=1
##
default HAVE_OPTION_TABLE=1
##
-## Move the default
LinuxBIOS
cmos range off of AMD RTC registers
+## Move the default
coreboot
cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@@
-122,13
+120,25
@@
default CONFIG_MAX_CPUS=2
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=0
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=0
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
#1G memory hole
#1G memory hole
-default
K8_E0
_MEM_HOLE_SIZEK=0x100000
+default
HW
_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_INIT=0
+
##
## Build code to setup a generic IOAPIC
##
##
## Build code to setup a generic IOAPIC
##
@@
-137,16
+147,16
@@
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="
s
2880"
+default MAINBOARD_PART_NUMBER="
S
2880"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880
###
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880
###
-###
LinuxBIOS
layout values
+###
coreboot
layout values
###
###
-## ROM_IMAGE_SIZE is the amount of space to allow
linuxBIOS
to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow
coreboot
to occupy.
default ROM_IMAGE_SIZE = 65536
##
default ROM_IMAGE_SIZE = 65536
##
@@
-165,14
+175,14
@@
default HEAP_SIZE=0x4000
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-##
LinuxBIOS
C code runs at this location in RAM
+##
Coreboot
C code runs at this location in RAM
##
default _RAMBASE=0x00004000
##
## Load the payload from the ROM
##
##
default _RAMBASE=0x00004000
##
## Load the payload from the ROM
##
-default CONFIG_ROM_
STREAM
= 1
+default CONFIG_ROM_
PAYLOAD
= 1
###
### Defaults of options that you may want to override in the target config file
###
### Defaults of options that you may want to override in the target config file
@@
-214,7
+224,7
@@
default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
default TTYS0_LCS=0x3
##
-### Select the
linuxBIOS
loglevel
+### Select the
coreboot
loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately