architecture beh of display is
type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
architecture beh of display is
type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT, S_COUNTUP, S_GETCH,
- S_PUTCH, S_WAIT, S_NOP1);
+ S_CR1, S_NL1, S_PUTCH1, S_PUTCH2, S_WAIT, S_NOP1);
signal state_int, state_next : DISPLAY_STATE;
signal d_zeile_int, d_zeile_next : hzeile;
signal d_spalte_int, d_spalte_next : hspalte;
signal d_get_int, d_get_next : std_logic;
signal command_int, command_next : std_logic_vector(7 downto 0);
signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
signal state_int, state_next : DISPLAY_STATE;
signal d_zeile_int, d_zeile_next : hzeile;
signal d_spalte_int, d_spalte_next : hspalte;
signal d_get_int, d_get_next : std_logic;
signal command_int, command_next : std_logic_vector(7 downto 0);
signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
-- next state
process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int,
-- next state
process(state_int, d_new_result, d_new_eingabe, d_done, free, d_spalte_int,
if d_new_eingabe = '1' then
state_next <= S_NEW_INPUT;
end if;
if d_new_result = '1' then
state_next <= S_NEW_RESULT;
end if;
if d_new_eingabe = '1' then
state_next <= S_NEW_INPUT;
end if;
if d_new_result = '1' then
state_next <= S_NEW_RESULT;
end if;
when S_NEW_RESULT =>
d_spalte_next <= (others => '0');
case d_zeile_int is
when "11111" => d_zeile_next <= "00000";
when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
end case;
when S_NEW_RESULT =>
d_spalte_next <= (others => '0');
case d_zeile_int is
when "11111" => d_zeile_next <= "00000";
when others => d_zeile_next <= std_logic_vector(unsigned(d_zeile_int) + 1);
end case;