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Remove XIP_ROM_BASE
[coreboot.git]
/
src
/
cpu
/
intel
/
model_6fx
/
cache_as_ram.inc
diff --git
a/src/cpu/intel/model_6fx/cache_as_ram.inc
b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 2ba187271e7a30e22910e664a7c4d1027afcda1f..dfc4f3b2b9f49b1e910115ad9e653f98716310c6 100644
(file)
--- a/
src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/
src/cpu/intel/model_6fx/cache_as_ram.inc
@@
-105,7
+105,7
@@
clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
orl $(1 << 30), %eax
movl %eax, %cr0
-#if
defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if
CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
@@
-122,7
+122,7
@@
clear_mtrrs:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE
&& CONFIG_XIP_ROM_BASE
*/
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
/* Enable cache. */
movl %cr0, %eax