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Intel model_106cx: Use symbolic names for MTRR bits
[coreboot.git]
/
src
/
cpu
/
intel
/
model_106cx
/
cache_as_ram.inc
diff --git
a/src/cpu/intel/model_106cx/cache_as_ram.inc
b/src/cpu/intel/model_106cx/cache_as_ram.inc
index da14db22ae978bc8772b70f9f6a286467731731f..824e3411100e75b6bcc0dfa5209dbcffb5c9937e 100644
(file)
--- a/
src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/
src/cpu/intel/model_106cx/cache_as_ram.inc
@@
-63,14
+63,14
@@
clear_mtrrs:
/* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx
/* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx
- movl $(~(
(CACHE_AS_RAM_SIZE - 1)) | (1 << 11)
), %eax
+ movl $(~(
CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid
), %eax
xorl %edx, %edx
wrmsr
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
xorl %edx, %edx
wrmsr
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
- orl $
(1 << 11)
, %eax
+ orl $
MTRRdefTypeEn
, %eax
wrmsr
/* Enable L2 cache. */
wrmsr
/* Enable L2 cache. */
@@
-98,29
+98,24
@@
clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
orl $(1 << 30), %eax
movl %eax, %cr0
-#if
defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if
CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
/*
/*
- * IMPORTANT: The two lines below can _not_ be written like this:
- * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $REAL_XIP_ROM_BASE, %eax
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
xorl %edx, %edx
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
xorl %edx, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) |
0x800
), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) |
MTRRphysMaskValid
), %eax
wrmsr
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE
&& CONFIG_XIP_ROM_BASE
*/
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
/* Enable cache. */
movl %cr0, %eax
@@
-160,7
+155,7
@@
clear_mtrrs:
/* Disable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
/* Disable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
- andl $(~
(1 << 11)
), %eax
+ andl $(~
MTRRdefTypeEn
), %eax
wrmsr
post_code(0x31)
wrmsr
post_code(0x31)
@@
-201,7
+196,7
@@
clear_mtrrs:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(1024 * 1024 - 1) |
(1 << 11)
), %eax
+ movl $(~(1024 * 1024 - 1) |
MTRRphysMaskValid
), %eax
xorl %edx, %edx
wrmsr
xorl %edx, %edx
wrmsr
@@
-217,7
+212,7
@@
clear_mtrrs:
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
- orl $
(1 << 11)
, %eax
+ orl $
MTRRdefTypeEn
, %eax
wrmsr
post_code(0x3b)
wrmsr
post_code(0x3b)