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Remove XIP_ROM_BASE
[coreboot.git]
/
src
/
cpu
/
intel
/
car
/
cache_as_ram.inc
diff --git
a/src/cpu/intel/car/cache_as_ram.inc
b/src/cpu/intel/car/cache_as_ram.inc
index 26fec6e5946122794ac49b906042676e69faf41e..7742a68225e7392a30e98cb80921e33f5180ddd3 100644
(file)
--- a/
src/cpu/intel/car/cache_as_ram.inc
+++ b/
src/cpu/intel/car/cache_as_ram.inc
@@
-229,7
+229,7
@@
clear_fixed_var_mtrr_out:
simplemask CacheSize, 0
wrmsr
simplemask CacheSize, 0
wrmsr
-#if
defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if
CONFIG_XIP_ROM_SIZE
/*
* Enable write base caching so we can do execute in place (XIP)
/*
* Enable write base caching so we can do execute in place (XIP)
@@
-250,7
+250,7
@@
clear_fixed_var_mtrr_out:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE
&& CONFIG_XIP_ROM_BASE
*/
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
/* Enable cache. */
movl %cr0, %eax